From owner-ddd-bugs@ibr.cs.tu-bs.de  Tue Dec 15 15:22:04 1998
From: Lieven Gesquiere <gesquiel@sebb.bel.alcatel.be>
Subject: [ddd-bugs] graphical display of huge structures
To: DDD Bug Report Address <bug-ddd@gnu.org>
Date: Tue, 15 Dec 1998 15:19:36 +0100
Reply-To: lieven.gesquiere@alcatel.be
Organization: ASD - WE4 - ADSL Technology
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[1  <text/plain; us-ascii (7bit)>]
Hoi,

I've the following problem with DDD-3.3.1. The bug is not version specific since
the problem occurs in older versions too.

I defined a huge structure in C using bitfields which is a (complete) memorymap
of a chips internal registers.

The attached headerfile (CSR.h) contains the definition of the structure called
'CSR'

Here is an example C file that uses the structure:

--------------------------------------------
typedef unsigned long T32;
#include "CSR.h"

main()
{
  CSR a;

  printf ("%d\n", a.SCH_PRI.TUN_ENA7);
}
--------------------------------------------
When you display the variable 'a' graphically, not all fields are displayed.
Although if requested to gdb manually, gdb prints all fields. I looks like there
is a limit in DDD in parsing the output of gdb.

Question: Is there such a limit? And if, where do I increase it ? 
          Or does DDD stop because of some bug ? 

Thanks for help,

Lieven
-- 
--------------------------------------------------
Lieven Gesquiere       lieven.gesquiere@alcatel.be
Alcatel Bell, F. Wellesplein 1, Antwerpen, Belgium
Phone: +32-3-240-8135          Fax: +32-3-240-9920
Intranet Server : http://www2.sebb.bel.alcatel.be/
[2 CSR.h <text/plain; us-ascii (7bit)>]
#ifndef CSR_H
#define CSR_H


typedef struct TCLOCK {
  T32 CLOCK               :32;
} TCLOCK;
typedef TCLOCK *PCLOCK;


typedef struct TALARM1 {
  T32 ALARM1              :32;
} TALARM1;
typedef TALARM1 *PALARM1;


typedef struct TSYS_STAT {
  T32 RSRVD1              :15;
  T32 PCI_BUS_STATUS      :5;
  T32 RAMMODE             :1;
  T32 PROCMODE            :1;
  T32 FRCFG               :2;
  T32 VERSION             :4;
  T32 DEVICE              :4;
} TSYS_STAT;
typedef TSYS_STAT *PSYS_STAT;


typedef struct TCONFIG0 {
  T32 LP_ENABLE           :1;
  T32 GLOBAL_RESET        :1;
  T32 PCI_MSTR_RESET      :1;
  T32 PCI_ERR_RESET       :1;
  T32 RSRVD1              :2;
  T32 PHY2_EN             :1;
  T32 INT_LBANK           :1;
  T32 RSRVD2              :1;
  T32 PCI_READ_MULTI      :1;
  T32 PCI_ARB             :1;
  T32 STATMODE            :5;
  T32 FR_RMODE            :1;
  T32 FR_LOOP             :1;
  T32 UTOPIA_MODE         :1;
  T32 ENDIAN              :1;
  T32 LP_BWAIT            :1;
  T32 MEMCTRL             :1;
  T32 BANKSIZE            :3;
  T32 DIVIDER             :7;
} TCONFIG0;
typedef TCONFIG0 *PCONFIG0;


typedef struct TINT_DELAY {
  T32 RSRVD1              :21;
  T32 TIMER_LOC           :1;
  T32 EN_TIMER            :1;
  T32 EN_STAT_CNT         :1;
  T32 STAT_CNT            :8;
} TINT_DELAY;
typedef TINT_DELAY *PINT_DELAY;

/*
 * ###########################################################################
 * ##                                                                        #
 * ##  13.3 SEGMENTATION REGISTERS                                           #
 * ##                                                                        #
 * ###########################################################################
 */


typedef struct TSEG_CTRL {
  T32 SEG_ENABLE          :1;
  T32 SEG_RESET           :1;
  T32 VBR_OFFSET          :3;
  T32 SEG_GFC             :1;
  T32 DBL_SLOT            :1;
  T32 CBR_TUN             :1;
  T32 ADV_ABR_TMPLT       :1;
  T32 RSRVD1              :7;
  T32 TX_FIFO_LEN         :4;
  T32 CLP0_EOM            :1;
  T32 OAM_STAT_ID         :5;
  T32 SEG_ST_HALT         :1;
  T32 SEG_LS_DIS          :1;
  T32 SEG_HS_DIS          :1;
  T32 TX_RND              :1;
  T32 TR_SIZE             :2;
} TSEG_CTRL;
typedef TSEG_CTRL *PSEG_CTRL;


typedef struct TSEG_VBASE {
  T32 SEG_SCHB            :16;
  T32 SEG_VCCB            :16;
} TSEG_VBASE;
typedef TSEG_VBASE *PSEG_VBASE;


typedef struct TSEG_PMBASE {
  T32 SEG_BCKB            :16;
  T32 SEG_PMB             :16;
} TSEG_PMBASE;
typedef TSEG_PMBASE *PSEG_PMBASE;


typedef struct TSEG_TXBASE {
  T32 SEG_TXB             :16;
  T32 RSRVD1              :3;
  T32 XMIT_INTERVAL       :8;
  T32 TX_EN               :5;
} TSEG_TXBASE;
typedef TSEG_TXBASE *PSEG_TXBASE;

/*
 * ###########################################################################
 * ##                                                                        #
 * ##  13.4 SCHEDULER REGISTERS                                              #
 * ##                                                                        #
 * ###########################################################################
 */


typedef struct TSCH_PRI {
  T32 QPCR_ENA7           :1;
  T32 QPCR_ENA6           :1;
  T32 QPCR_ENA5           :1;
  T32 QPCR_ENA4           :1;
  T32 QPCR_ENA3           :1;
  T32 QPCR_ENA2           :1;
  T32 QPCR_ENA1           :1;
  T32 QPCR_ENA0           :1;
  T32 RSRVD1              :1;
  T32 TUN_ENA7            :1;
  T32 GFC7                :1;
  T32 RSRVD2              :1;
  T32 TUN_ENA6            :1;
  T32 GFC6                :1;
  T32 RSRVD3              :1;
  T32 TUN_ENA5            :1;
  T32 GFC5                :1;
  T32 RSRVD4              :1;
  T32 TUN_ENA4            :1;
  T32 GFC4                :1;
  T32 RSRVD5              :1;
  T32 TUN_ENA3            :1;
  T32 GFC3                :1;
  T32 RSRVD6              :1;
  T32 TUN_ENA2            :1;
  T32 GFC2                :1;
  T32 RSRVD7              :1;
  T32 TUN_ENA1            :1;
  T32 GFC1                :1;
  T32 RSRVD8              :1;
  T32 TUN_ENA0            :1;
  T32 GFC0                :1;
} TSCH_PRI;
typedef TSCH_PRI *PSCH_PRI;


typedef struct TSCH_SIZE {
  T32 TBL_SIZE            :16;
  T32 RSRVD1              :2;
  T32 SLOT_PER            :14;
} TSCH_SIZE;
typedef TSCH_SIZE *PSCH_SIZE;


typedef struct TSCH_ABR_MAX {
  T32 RSRVD1              :16;
  T32 VCC_MAX             :16;
} TSCH_ABR_MAX;
typedef TSCH_ABR_MAX *PSCH_ABR_MAX;


typedef struct TSCH_ABR_CON {
  T32 ABR_TRM             :16;
  T32 ABR_ADTF            :16;
} TSCH_ABR_CON;
typedef TSCH_ABR_CON *PSCH_ABR_CON;


typedef struct TSCH_ABRBASE {
  T32 RSRVD1              :3;
  T32 OOR_EN              :1;
  T32 OOR_INT             :12;
  T32 SCH_ABRB            :16;
} TSCH_ABRBASE;
typedef TSCH_ABRBASE *PSCH_ABRBASE;


typedef struct TSCH_CNG {
  T32 FBQ_CNG             :32;
} TSCH_CNG;
typedef TSCH_CNG *PSCH_CNG;


typedef struct TPCR_QUE_INT01 {
  T32 QPCR_INT1           :16;
  T32 QPCR_INT0           :16;
} TPCR_QUE_INT01;
typedef TPCR_QUE_INT01 *PPCR_QUE_INT01;


typedef struct TPCR_QUE_INT23 {
  T32 QPCR_INT3           :16;
  T32 QPCR_INT2           :16;
} TPCR_QUE_INT23;
typedef TPCR_QUE_INT23 *PPCR_QUE_INT23;

/*
 * ###########################################################################
 * ##                                                                        #
 * ##  13.5 REASSEMBLY REGISTERS                                             #
 * ##                                                                        #
 * ###########################################################################
 */


typedef struct TRSM_CTRL0 {
  T32 RSM_ENABLE          :1;
  T32 RSM_RESET           :1;
  T32 RSRVD1              :1;
  T32 VPI_MASK            :1;
  T32 RSRVD2              :4;
  T32 RSRVD3              :6;
  T32 RSM_PHALT           :1;
  T32 RSRVD4              :1;
  T32 FWALL_EN            :1;
  T32 RSM_FBQ_DIS         :1;
  T32 RSM_STAT_DIS        :1;
  T32 GTO_EN              :1;
  T32 MAX_LEN             :7;
  T32 GDIS_PRI            :5;
} TRSM_CTRL0;
typedef TRSM_CTRL0 *PRSM_CTRL0;


typedef struct TRSM_CTRL1 {
  T32 EN_PROG_BLK_SZ      :1;
  T32 VCI_IT_BLK_SZ       :3;
  T32 RSRVD1              :4;
  T32 RSRVD2              :4;
  T32 RSRVD3              :3;
  T32 RSRVD4              :4;
  T32 OAM_FF_DSC          :1;
  T32 OAM_EN              :1;
  T32 OAM_QU_EN           :1;
  T32 OAM_BFR_QU          :5;
  T32 OAM_STAT_QU         :5;
} TRSM_CTRL1;
typedef TRSM_CTRL1 *PRSM_CTRL1;


typedef struct TRSM_FQBASE {
  T32 FBQ1_BASE           :16;
  T32 FBQ0_BASE           :16;
} TRSM_FQBASE;
typedef TRSM_FQBASE *PRSM_FQBASE;


typedef struct TRSM_FQCTRL {
  T32 RSRVD1              :16;
  T32 FBQ_SIZE            :2;
  T32 FWD_RND             :1;
  T32 FBQ0_RTN            :1;
  T32 FWD_EN              :4;
  T32 FBQ_UD_INT          :8;
} TRSM_FQCTRL;
typedef TRSM_FQCTRL *PRSM_FQCTRL;


typedef struct TRSM_TBASE {
  T32 RSM_VCCB            :16;
  T32 RSM_ITB             :16;
} TRSM_TBASE;
typedef TRSM_TBASE *PRSM_TBASE;


typedef struct TRSM_TO {
  T32 RSM_TO_PER          :16;
  T32 RSM_TO_CNT          :16;
} TRSM_TO;
typedef TRSM_TO *PRSM_TO;


typedef struct TRS_QBASE {
  T32 RSRVD1              :14;
  T32 RS_SIZE             :2;
  T32 RS_QBASE            :16;
} TRS_QBASE;
typedef TRS_QBASE *PRS_QBASE;

/*
 * ###########################################################################
 * ##                                                                        #
 * ##  13.6 CONTROL/STATUS REGISTERS                                         #
 * ##                                                                        #
 * ###########################################################################
 */


typedef struct TCELL_XMIT_CNT {
  T32 CELL_XMIT_CNT       :32;
} TCELL_XMIT_CNT;
typedef TCELL_XMIT_CNT *PCELL_XMIT_CNT;


typedef struct TCELL_RCVD_CNT {
  T32 CELL_RCVD_CNT       :32;
} TCELL_RCVD_CNT;
typedef TCELL_RCVD_CNT *PCELL_RCVD_CNT;


typedef struct TCELL_DSC_CNT {
  T32 CELL_DSC_CNT        :32;
} TCELL_DSC_CNT;
typedef TCELL_DSC_CNT *PCELL_DSC_CNT;


typedef struct TAAL5_DSC_CNT {
  T32 RSRVD1              :16;
  T32 AAL5_DSC_CNT        :16;
} TAAL5_DSC_CNT;
typedef TAAL5_DSC_CNT *PAAL5_DSC_CNT;


typedef struct THOST_MBOX {
  T32 HOST_MBOX           :32;
} THOST_MBOX;
typedef THOST_MBOX *PHOST_MBOX;


typedef struct THOST_ST_WR {
  T32 RSM_HS_WRITE        :16;
  T32 SEG_HS_WRITE        :16;
} THOST_ST_WR;
typedef THOST_ST_WR *PHOST_ST_WR;


typedef struct TLP_MBOX {
  T32 LP_MBOX             :32;
} TLP_MBOX;
typedef TLP_MBOX *PLP_MBOX;


typedef struct THOST_ISTAT0 {
  T32 PFAIL               :1;
  T32 PHY_INTR            :1;
  T32 RSRVD1              :1;
  T32 HOST_MBOX_          :1;
  T32 LP_MBOX_READ        :1;
  T32 RSRVD2              :1;
  T32 RSRVD3              :2;
  T32 RSRVD4              :1;
  T32 HSTAT1              :1;
  T32 RSRVD5              :3;
  T32 GFC_LINK            :1;
  T32 RSM_RUN             :1;
  T32 RSM_HS_WRITE        :1;
  T32 RSM_LS_WRITE        :1;
  T32 RSRVD6              :3;
  T32 SEG_RUN             :1;
  T32 SEG_HS_WRITE        :1;
  T32 SEG_LS_WRITE        :1;
  T32 RSRVD7              :5;
  T32 AAL5_DSC_RLOVR      :1;
  T32 CELL_DSC_RLOVR      :1;
  T32 CELL_RCVD_RLOVR     :1;
  T32 CELL_XMT_RLOVR      :1;
} THOST_ISTAT0;
typedef THOST_ISTAT0 *PHOST_ISTAT0;


typedef struct THOST_ISTAT1 {
  T32 PCI_BUS_EROR        :1;
  T32 RSRVD1              :4;
  T32 DMA_AFULL           :1;
  T32 FR_PAR_ERR          :1;
  T32 FR_SYNC_ERR         :1;
  T32 RSRVD2              :8;
  T32 RS_QUEUE_FULL       :1;
  T32 RSM_OVFL            :1;
  T32 RSM_HS_FULL         :1;
  T32 RSM_LS_FULL         :1;
  T32 RSM_HF_EMPT         :1;
  T32 RSM_LF_EMPT         :1;
  T32 RSRVD3              :7;
  T32 SEG_UNFL            :1;
  T32 SEG_HS_FULL         :1;
  T32 SEG_LS_FULL         :1;
} THOST_ISTAT1;
typedef THOST_ISTAT1 *PHOST_ISTAT1;


typedef struct THOST_IMASK0 {
  T32 EN_PFAIL            :1;
  T32 EN_PHY_INTR         :1;
  T32 RSRVD1              :1;
  T32 EN_HOST_MBOX_WRITTEN:1;
  T32 EN_LP_MBOX_READ     :1;
  T32 RSRVD2              :1;
  T32 RSRVD3              :2;
  T32 RSRVD4              :1;
  T32 EN_HSTAT1           :1;
  T32 RSRVD5              :3;
  T32 EN_GFC_LINK         :1;
  T32 EN_RSM_RUN          :1;
  T32 EN_RSM_HS_WRITE     :1;
  T32 EN_RSM_LS_WRITE     :1;
  T32 RSRVD6              :3;
  T32 EN_SEG_RUN          :1;
  T32 EN_SEG_HS_WRITE     :1;
  T32 EN_SEG_LS_WRITE     :1;
  T32 RSRVD7              :5;
  T32 EN_AAL5_DSC_RLOVR   :1;
  T32 EN_CELL_DSC_RLOVR   :1;
  T32 EN_CELL_RCVD_RLOVR  :1;
  T32 EN_CELL_XMIT_RLOVR  :1;
} THOST_IMASK0;
typedef THOST_IMASK0 *PHOST_IMASK0;


typedef struct THOST_IMASK1 {
  T32 EN_PCI_BUS_ERROR    :1;
  T32 RSRVD1              :4;
  T32 EN_DMA_AFULL        :1;
  T32 EN_FR_PAR_ERR       :1;
  T32 EN_FR_SYNC_ERR      :1;
  T32 RSRVD2              :8;
  T32 EN_RSQUEUE_FULL     :1;
  T32 EN_RSM_OVFL         :1;
  T32 EN_RSM_HS_FULL      :1;
  T32 EN_RSM_LS_FULL      :1;
  T32 EN_RSM_HF_EMPT      :1;
  T32 EN_RSM_LF_EMPT      :1;
  T32 RSRVD3              :7;
  T32 EN_SEG_UNFL         :1;
  T32 EN_SEG_HS_FULL      :1;
  T32 EN_SEG_LS_FULL      :1;
} THOST_IMASK1;
typedef THOST_IMASK1 *PHOST_IMASK1;


typedef struct TLP_ISTAT0 {
  T32 RTC_OVFL            :1;
  T32 ALARM1              :1;
  T32 RSRVD1              :1;
  T32 LP_MBOX_WRITTEN     :1;
  T32 HOST_MBOX_READ      :1;
  T32 RSRVD2              :1;
  T32 RSRVD3              :2;
  T32 RSRVD4              :1;
  T32 LSTAT1              :1;
  T32 RSRVD5              :3;
  T32 GFC_LINK            :1;
  T32 RSM_RUN             :1;
  T32 RSM_HS_WRITE        :1;
  T32 RSM_LS_WRITE        :1;
  T32 RSRVD6              :3;
  T32 SEG_RUN             :1;
  T32 SEG_HS_WRITE        :1;
  T32 SEG_LS_WRITE        :1;
  T32 RSRVD7              :5;
  T32 AAL5_DSC_RLOVR      :1;
  T32 CELL_DSC_RLOVR      :1;
  T32 CELL_RCVD_RLOVR     :1;
  T32 CELL_XMIT_RLOVR     :1;
} TLP_ISTAT0;
typedef TLP_ISTAT0 *PLP_ISTAT0;


typedef struct TLP_ISTAT1 {
  T32 PCI_BUS_EROR        :1;
  T32 RSRVD1              :4;
  T32 DMA_AFULL           :1;
  T32 FR_PAR_ERR          :1;
  T32 FR_SYNC_ERR         :1;
  T32 RSRVD2              :8;
  T32 RS_QUEUE_FULL       :1;
  T32 RSM_OVFL            :1;
  T32 RSM_HS_FULL         :1;
  T32 RSM_LS_FULL         :1;
  T32 RSM_HF_EMPT         :1;
  T32 RSM_LF_EMPT         :1;
  T32 RSRVD3              :7;
  T32 SEG_UNFL            :1;
  T32 SEG_HS_FULL         :1;
  T32 SEG_LS_FULL         :1;
} TLP_ISTAT1;
typedef TLP_ISTAT1 *PLP_ISTAT1;


typedef struct TLP_IMASK0 {
  T32 EN_RTC_OVFL         :1;
  T32 EN_ALARM1           :1;
  T32 RSRVD1              :1;
  T32 EN_LP_MBOX_WRITTEN  :1;
  T32 EN_HOST_MBOX_READ   :1;
  T32 RSRVD2              :1;
  T32 RSRVD3              :2;
  T32 RSRVD4              :1;
  T32 EN_LSTAT1           :1;
  T32 RSRVD5              :3;
  T32 EN_GFC_LINK         :1;
  T32 EN_RSM_RUN          :1;
  T32 EN_RSM_HS_WRITE     :1;
  T32 EN_RSM_LS_WRITE     :1;
  T32 RSRVD6              :3;
  T32 EN_SEG_RUN          :1;
  T32 EN_SEG_HS_WRITE     :1;
  T32 EN_SEG_LS_WRITE     :1;
  T32 RSRVD7              :5;
  T32 EN_AAL5_DSC_RLOVR   :1;
  T32 EN_CELL_DSC_RLOVR   :1;
  T32 EN_CELL_RCVD_RLOVR  :1;
  T32 EN_CELL_XMIT_RLOVR  :1;
} TLP_IMASK0;
typedef TLP_IMASK0 *PLP_IMASK0;


typedef struct TLP_IMASK1 {
  T32 EN_PCI_BUS_ERROR    :1;
  T32 RSRVD1              :4;
  T32 EN_DMA_AFULL        :1;
  T32 EN_FR_PAR_ERR       :1;
  T32 EN_FR_SYNC_ERR      :1;
  T32 RSRVD2              :8;
  T32 EN_RSQUEUE_FULL     :1;
  T32 EN_RSM_OVFL         :1;
  T32 EN_RSM_HS_FULL      :1;
  T32 EN_RSM_LS_FULL      :1;
  T32 EN_RSM_HS_EMPT      :1;
  T32 EN_RSM_LS_EMPT      :1;
  T32 RSRVD3              :7;
  T32 EN_SEG_UNFL         :1;
  T32 EN_SEG_HS_FULL      :1;
  T32 EN_SEG_LS_FULL      :1;
} TLP_IMASK1;
typedef TLP_IMASK1 *PLP_IMASK1;

/*
 * ###########################################################################
 * ##                                                                        #
 * ##  13.1 CSR REGISTERS                                                    #
 * ##                                                                        #
 * ###########################################################################
 */

typedef struct {
  TCLOCK         CLOCK;
  TALARM1        ALARM1;
                 
  T32            RSRVD1;        /* Reserved */
                 
  TSYS_STAT      SYS_STAT;
                 
  T32            RSRVD2;        /* Reserved */
                 
  TCONFIG0       CONFIG0;
                 
  T32            RSRVD3;        /* Reserved */
                    
  TINT_DELAY     INT_DELAY;
                    
  T32            RSRVD4[(0x80-0x20)/4];  /* Reserved */
                    
  TSEG_CTRL      SEG_CTRL;
  TSEG_VBASE     SEG_VBASE;
  TSEG_PMBASE    SEG_PMBASE;
  TSEG_TXBASE    SEG_TXBASE;
                    
  T32            RSRVD5[(0xa0-0x90)/4];  /* Reserved */
                    
  TSCH_PRI       SCH_PRI;
                    
  T32            RSRVD6;        /* Reserved */
                    
  TSCH_SIZE      SCH_SIZE;
                    
  T32            RSRVD7;        /* Reserved */                
                 
  TSCH_ABR_MAX   SCH_ABR_MAX;
  TSCH_ABR_CON   SCH_ABR_CON;
  TSCH_ABRBASE   SCH_ABRBASE;
  TSCH_CNG       SCH_CNG;    
  TPCR_QUE_INT01 PCR_QUE_INT01;
  TPCR_QUE_INT23 PCR_QUE_INT23;
                 
  T32            RSRVD8[(0xf0-0xc8)/4];  /* Reserved */
                 
  TRSM_CTRL0     RSM_CTRL0;
  TRSM_CTRL1     RSM_CTRL1;
  TRSM_FQBASE    RSM_FQBASE;
  TRSM_FQCTRL    RSM_FQCTRL;
  TRSM_TBASE     RSM_TBASE;
  TRSM_TO        RSM_TO;
  TRS_QBASE      RS_QBASE;
                 
  T32            RSRVD9[(0x160-0x10c)/4];  /* Reserved */
                 
  TCELL_XMIT_CNT CELL_XMIT_CNT;
  TCELL_RCVD_CNT CELL_RCVD_CNT;
  TCELL_DSC_CNT  CELL_DSC_CNT;
  TAAL5_DSC_CNT  AAL5_DSC_CNT;
                 
  T32            RSRVD10[(0x1a0-0x170)/4];  /* Reserved */
                 
  THOST_MBOX     HOST_MBOX;
  THOST_ST_WR    HOST_ST_WR;
                 
  T32            RSRVD11[(0x1b0-0x1a8)/4];  /* Reserved */  
                 
  TLP_MBOX       LP_MBOX;
                 
  T32            RSRVD12[(0x1c0-0x1b4)/4];  /* Reserved */  
                 
  THOST_ISTAT0   HOST_ISTAT0;
  THOST_ISTAT1   HOST_ISTAT1;
                 
  T32            RSRVD13[(0x1d0-0x1c8)/4];  /* Reserved */  
                 
  THOST_IMASK0   HOST_IMASK0;
  THOST_IMASK1   HOST_IMASK1;
                 
  T32            RSRVD14[(0x1e0-0x1d8)/4];  /* Reserved */  
                 
  TLP_ISTAT0     LP_ISTAT0;
  TLP_ISTAT1     LP_ISTAT1;
                 
  T32            RSRVD15[(0x1f0-0x1e8)/4];  /* Reserved */  
                 
  TLP_IMASK0     LP_IMASK0;
  TLP_IMASK1     LP_IMASK1;
                 
  T32            RSRVD16[(0x200-0x1f8)/4];  /* Reserved */  
} CSR;

typedef struct {
  T32 CLOCK;
  T32 ALARM1;
      
  T32 RSRVD1;        /* Reserved */
      
  T32 SYS_STAT;
      
  T32 RSRVD2;        /* Reserved */
      
  T32 CONFIG0;
      
  T32 RSRVD3;        /* Reserved */
            
  T32 INT_DELAY;
            
  T32 RSRVD4[(0x80-0x20)/4];  /* Reserved */
            
  T32 SEG_CTRL;
  T32 SEG_VBASE;
  T32 SEG_PMBASE;
  T32 SEG_TXBASE;
            
  T32 RSRVD5[(0xa0-0x90)/4];  /* Reserved */
            
  T32 SCH_PRI;
            
  T32 RSRVD6;        /* Reserved */
            
  T32 SCH_SIZE;
            
  T32 RSRVD7;        /* Reserved */                
      
  T32 SCH_ABR_MAX;
  T32 SCH_ABR_CON;
  T32 SCH_ABRBASE;
  T32 SCH_CNG;    
  T32 PCR_QUE_INT01;
  T32 PCR_QUE_INT23;
      
  T32 RSRVD8[(0xf0-0xc8)/4];  /* Reserved */
      
  T32 RSM_CTRL0;
  T32 RSM_CTRL1;
  T32 RSM_FQBASE;
  T32 RSM_FQCTRL;
  T32 RSM_TBASE;
  T32 RSM_TO;
  T32 RS_QBASE;
      
  T32 RSRVD9[(0x160-0x10c)/4];  /* Reserved */
      
  T32 CELL_XMIT_CNT;
  T32 CELL_RCVD_CNT;
  T32 CELL_DSC_CNT;
  T32 AAL5_DSC_CNT;
      
  T32 RSRVD10[(0x1a0-0x170)/4];  /* Reserved */
      
  T32 HOST_MBOX;
  T32 HOST_ST_WR;
      
  T32 RSRVD11[(0x1b0-0x1a8)/4];  /* Reserved */  
      
  T32 LP_MBOX;
      
  T32 RSRVD12[(0x1c0-0x1b4)/4];  /* Reserved */  
      
  T32 HOST_ISTAT0;
  T32 HOST_ISTAT1;
      
  T32 RSRVD13[(0x1d0-0x1c8)/4];  /* Reserved */  
      
  T32 HOST_IMASK0;
  T32 HOST_IMASK1;
      
  T32 RSRVD14[(0x1e0-0x1d8)/4];  /* Reserved */  
      
  T32 LP_ISTAT0;
  T32 LP_ISTAT1;
      
  T32 RSRVD15[(0x1f0-0x1e8)/4];  /* Reserved */  
      
  T32 LP_IMASK0;
  T32 LP_IMASK1;
      
  T32 RSRVD16[(0x200-0x1f8)/4];  /* Reserved */  
} CSR32;

extern CSR *csr;
extern CSR32 *csr32;
/*
 * ###########################################################################
 * ##                                                                        #
 * ##  END OF FILE                                                           #
 * ##                                                                        #
 * ###########################################################################
 */
#endif

[3 log <text/plain; iso-8859-1 (quoted-printable)>]
DDD 3.1.1 (sparc-sun-solaris2.5.1), Copyright (C) 1998 TU Braunschweig.
Compiled with GCC 2.7.2.3, libstdc++ 2.7.2
Requires X11R5, Xt11R5, Motif 1.2.3 (OSF/Motif Version 1.2.3)
Includes DDD core, manual, app-defaults, XPM 3.4.6, Athena Panner
Built 1998-12-06 by the DDD Development Team <ddd@gnu.org>.
$  ddd a.out
+  /bin/sh -c 'exec gdb -q -fullname '\''a.out'\'''
#  Hello, world!
#  Starting GDB...
#  Running GDB (pid 26477, tty /dev/pts/27)...
#  Current language: c/c++
#  Another DDD is running (pid 26233)
<- "(gdb) "
-> "set prompt (gdb) \n"
<- "(gdb) "
-> "set height 0\n"
<- "(gdb) "
-> "set width 0\n"
<- "(gdb) "
-> "set annotate 1\n"
<- "No symbol \"annotate\" in current context.\n"
   "(gdb) "
-> " set verbose off\n"
<- "(gdb) "
-> "info line\n"
<- "No line number information available.\n"
   "(gdb) "
-> "list\n"
<- "1\ttypedef unsigned long T32;\n"
   "2\t#include \"CSR.h\"\n"
   "3\t\n"
   "4\tmain()\n"
   "5\t{\n"
   "6\t  CSR a;\n"
   "7\t  \n"
   "8\t  printf (\"%d\\n"
   "\", a.SCH_PRI.TUN_ENA7);\n"
   "9\t}(gdb) "
-> "info line\n"
<- "Line 9 of \"a.c\" starts at address 0x104c0 <main+32> and ends at 0x104c8 <__do_global_ctors_aux>.\n"
   "\032\032/home/users/gesquiel/a.c:9:105:beg:0x104c0\n"
   "(gdb) "
-> "output 4711\n"
<- "4711(gdb) "
-> "show language\n"
<- "The current source language is \"auto; currently c\".\n"
   "(gdb) "
-> "pwd\n"
<- "Working directory /home/users/gesquiel.\n"
   "(gdb) "
-> "info breakpoints\n"
<- "No breakpoints or watchpoints.\n"
   "(gdb) "
-> "show history filename\n"
<- "The filename in which to record the command history is \"/home/users/gesquiel/.gdb_history\".\n"
   "(gdb) "
-> "show history size\n"
<- "The size of the command history is 500.\n"
   "(gdb) "
#  Reading file "/home/users/gesquiel/a.c"...
#  Reading file "/home/users/gesquiel/a.c"...done.
#  File "/home/users/gesquiel/a.c" 9 lines, 113 characters
-> "info files\n"
<- "Symbols from \"/home/users/gesquiel/a.out\".\n"
   "Local exec file:\n"
   "\t`/home/users/gesquiel/a.out\', file type elf32-sparc.\n"
   "\tEntry point: 0x103c8\n"
   "\t0x000100d4 - 0x000100e5 is .interp\n"
   "\t0x000100e8 - 0x00010130 is .hash\n"
   "\t0x00010130 - 0x00010200 is .dynsym\n"
   "\t0x00010200 - 0x0001029e is .dynstr\n"
   "\t0x00010378 - 0x00010384 is .rela.bss\n"
   "\t0x00010384 - 0x000103b4 is .rela.plt\n"
   "\t0x000103b4 - 0x000103c8 is .init\n"
   "\t0x000103c8 - 0x0001052c is .text\n"
   "\t0x0001052c - 0x00010540 is .fini\n"
   "\t0x00010540 - 0x0001054c is .rodata\n"
   "\t0x0002054c - 0x00020554 is .ctors\n"
   "\t0x00020554 - 0x0002055c is .dtors\n"
   "\t0x0002055c - 0x000205c0 is .plt\n"
   "\t0x000205c0 - 0x000205d4 is .got\n"
   "\t0x000205d4 - 0x00020674 is .dynamic\n"
   "\t0x00020674 - 0x00020678 is .bss\n"
   "(gdb) "
-> "info program\n"
<- "The program being debugged is not being run.\n"
   "(gdb) "
-> "set confirm on\n"
<- "(gdb) "
-> "source /var/tmp/caaU2xN8_\n"
<- "(gdb) "
-> "info breakpoints\n"
<- "No breakpoints or watchpoints.\n"
   "(gdb) "
-> "# reset\n"
<- "(gdb) "
-> "info breakpoints\n"
<- "No breakpoints or watchpoints.\n"
   "(gdb) "
-> "display\n"
<- "(gdb) "
-> "info display\n"
<- "There are no auto-display expressions now.\n"
   "(gdb) "
-> "info files\n"
<- "Symbols from \"/home/users/gesquiel/a.out\".\n"
   "Local exec file:\n"
   "\t`/home/users/gesquiel/a.out\', file type elf32-sparc.\n"
   "\tEntry point: 0x103c8\n"
   "\t0x000100d4 - 0x000100e5 is .interp\n"
   "\t0x000100e8 - 0x00010130 is .hash\n"
   "\t0x00010130 - 0x00010200 is .dynsym\n"
   "\t0x00010200 - 0x0001029e is .dynstr\n"
   "\t0x00010378 - 0x00010384 is .rela.bss\n"
   "\t0x00010384 - 0x000103b4 is .rela.plt\n"
   "\t0x000103b4 - 0x000103c8 is .init\n"
   "\t0x000103c8 - 0x0001052c is .text\n"
   "\t0x0001052c - 0x00010540 is .fini\n"
   "\t0x00010540 - 0x0001054c is .rodata\n"
   "\t0x0002054c - 0x00020554 is .ctors\n"
   "\t0x00020554 - 0x0002055c is .dtors\n"
   "\t0x0002055c - 0x000205c0 is .plt\n"
   "\t0x000205c0 - 0x000205d4 is .got\n"
   "\t0x000205d4 - 0x00020674 is .dynamic\n"
   "\t0x00020674 - 0x00020678 is .bss\n"
   "(gdb) "
-> "info program\n"
<- "The program being debugged is not being run.\n"
   "(gdb) "
-> "help detach\n"
<- "Detach a process or file previously attached.\n"
   "If a process, it is no longer traced, and it continues its execution.  If you\n"
   "were debugging a file, the file is closed and gdb no longer accesses it.\n"
   "(gdb) "
-> "help run\n"
<- "Start debugged program.  You may specify arguments to give it.\n"
   "Args may include \"*\", or \"[...]\"; they are expanded using \"sh\".\n"
   "Input and output redirection with \">\", \"<\", or \">>\" are also allowed.\n"
   "\n"
   "With no arguments, uses arguments last specified (with \"run\" or \"set args\").\n"
   "To cancel previous arguments and run with no arguments,\n"
   "use \"set args\" without arguments.\n"
   "(gdb) "
#  Starting GDB...done.
#  Welcome to DDD 3.1.1 "Morning Sky" (sparc-sun-solaris2.5.1)
-> "help step\n"
<- "Step program until it reaches a different source line.\n"
   "Argument N means do this N times (or till program stops for another reason).\n"
   "(gdb) "
-> "help stepi\n"
<- "Step one instruction exactly.\n"
   "Argument N means do this N times (or till program stops for another reason).\n"
   "(gdb) "
-> "help next\n"
<- "Step program, proceeding through subroutine calls.\n"
   "Like the \"step\" command as long as subroutine calls do not happen;\n"
   "when they do, the call is treated as one instruction.\n"
   "Argument N means do this N times (or till program stops for another reason).\n"
   "(gdb) "
-> "help nexti\n"
<- "Step one instruction, but proceed through subroutine calls.\n"
   "Argument N means do this N times (or till program stops for another reason).\n"
   "(gdb) "
-> "help until\n"
<- "Execute until the program reaches a source line greater than the current\n"
   "or a specified line or address or function (same args as break command).\n"
   "Execution will also stop upon exit from the current stack frame.\n"
   "(gdb) "
-> "help finish\n"
<- "Execute until selected stack frame returns.\n"
   "Upon return, the value returned is printed and put in the value history.\n"
   "(gdb) "
-> "help cont\n"
<- "Continue program being debugged, after signal or breakpoint.\n"
   "If proceeding from breakpoint, a number N may be used as an argument,\n"
   "which means to set the ignore count of that breakpoint to N - 1 (so that\n"
   "the breakpoint won\'t break until the Nth time it is reached).\n"
   "(gdb) "
-> "help signal\n"
<- "Continue program giving it signal specified by the argument.\n"
   "An argument of \"0\" means continue program without giving it a signal.\n"
   "(gdb) "
-> "help kill\n"
<- "Kill execution of program being debugged.\n"
   "(gdb) "
-> "help up\n"
<- "Select and print stack frame that called this one.\n"
   "An argument says how many frames up to go.\n"
   "(gdb) "
-> "help down\n"
<- "Select and print stack frame called by this one.\n"
   "An argument says how many frames down to go.\n"
   "(gdb) "
-> "info source\n"
<- "Current source file is a.c\n"
   "Compilation directory is /home/users/gesquiel/\n"
   "Located in /home/users/gesquiel/a.c\n"
   "Contains 9 lines.\n"
   "Source language is c.\n"
   "(gdb) "
-> "break a.c:8\n"
<- "Breakpoint 1 at 0x104a4: file a.c, line 8.\n"
   "(gdb) "
-> "info breakpoints\n"
<- "Num Type           Disp Enb Address    What\n"
   "1   breakpoint     keep y   0x000104a4 in main at a.c:8\n"
   "(gdb) "
-> "set environment TERM dumb\n"
<- "(gdb) "
-> "r\n"
<- "Starting program: /home/users/gesquiel/a.out \n"
<- "warning: "
<- "Unable to find dynamic linker breakpoint function."
<- "\n"
<- "warning: "
<- "GDB will be unable to debug shared library initializers"
<- "\n"
<- "warning: "
<- "and track explicitly loaded dynamic code."
<- "\n"
<- "\n"
   "Breakpoint 1, "
<- "main"
<- " ("
<- ")"
<- " at "
<- "a.c"
<- ":"
<- "8"
<- "\n"
<- "\032\032"
<- "/home/users/gesquiel/a.c:8:66:beg:0x104a4\n"
   "(gdb) "
-> "info breakpoints\n"
<- "Num Type           Disp Enb Address    What\n"
   "1   breakpoint     keep y   0x000104a4 in main at a.c:8\n"
   "\tbreakpoint already hit 1 time\n"
   "(gdb) "
-> "output a\n"
<- "{CLOCK = {CLOCK = 8191}, ALARM1 = {ALARM1 = 0}, RSRVD1 = 0, SYS_STAT = {RSRVD1 = 30655, PCI_BUS_STATUS = 24, RAMMODE = 0, PROCMODE = 1, FRCFG = 0, VERSION = 10, DEVICE = 4}, RSRVD2 = 1, CONFIG0 = {LP_ENABLE = 0, GLOBAL_RESET = 0, PCI_MSTR_RESET = 0, PCI_ERR_RESET = 0, RSRVD1 = 0, PHY2_EN = 0, INT_LBANK = 0, RSRVD2 = 0, PCI_READ_MULTI = 0, PCI_ARB = 0, STATMODE = 2, FR_RMODE = 0, FR_LOOP = 0, UTOPIA_MODE = 0, ENDIAN = 0, LP_BWAIT = 0, MEMCTRL = 0, BANKSIZE = 0, DIVIDER = 0}, RSRVD3 = 4294836223, INT_DELAY = {RSRVD1 = 1961480, TIMER_LOC = 1, EN_TIMER = 0, EN_STAT_CNT = 0, STAT_CNT = 204}, RSRVD4 = {5, 212, 65748, 4017946624, 4026527152, 4017955812, 0, 0, 0, 0, 0, 0, 0, 67192, 66504, 65588, 5, 32, 65536, 4018111652, 1, 131072, 4294836223, 4017117660}, SEG_CTRL = {SEG_ENABLE = 0, SEG_RESET = 0, VBR_OFFSET = 0, SEG_GFC = 0, DBL_SLOT = 0, CBR_TUN = 0, ADV_ABR_TMPLT = 0, RSRVD1 = 0, TX_FIFO_LEN = 0, CLP0_EOM = 0, OAM_STAT_ID = 0, SEG_ST_HALT = 0, SEG_LS_DIS = 0, SEG_HS_DIS = 0, TX_RND = 0, TR_SIZE = 0}, SEG_VBASE = {SEG_SCHB = 0, SEG_VCCB = 0}, SEG_PMBASE = {SEG_BCKB = 0, SEG_PMB = 0}, SEG_TXBASE = {SEG_TXB = 65535, RSRVD1 = 7, XMIT_INTERVAL = 255, TX_EN = 31}, RSRVD5 = {4017946624, 4026531789, 4243, 4243}, SCH_PRI = {QPCR_ENA7 = 0, QPCR_ENA6 = 0, QPCR_ENA5 = 0, QPCR_ENA4 = 0, QPCR_ENA3 = 0, QPCR_ENA2 = 0, QPCR_ENA1 = 0, QPCR_ENA0 = 0, RSRVD1 = 0, TUN_ENA7 = 0, GFC7 = 0, RSRVD2 = 0, TUN_ENA6 = 0, GFC6 = 0, RSRVD3 = 0, TUN_ENA5 = 0, GFC5 = 0, RSRVD4 = 0, TUN_ENA4 = 0, GFC4 = 0, RSRVD5 = 1, TUN_ENA3 = 1, GFC3 = 1, RSRVD6 = 0, TUN_ENA2 = 0, GFC2 = 0, RSRVD7 = 0, TUN_ENA1 = 1, GFC1 = 1, RSRVD8 = 0, TUN_ENA0 = 1, GFC0 = 0}, RSRVD6 = 4026527732, SCH_SIZE = {TBL_SIZE = 0, RSRVD1 = 0, SLOT_PER = 768}, RSRVD7 = 65588, SCH_ABR_MAX = {RSRVD1 = 61439, VCC_MAX = 61084}, SCH_ABR_CON = {ABR_TRM = 61309, ABR_ADTF = 5481}, SCH_ABRBASE = {RSRVD1 = 0, OOR_EN = 0, OOR_INT = 0, SCH_ABRB = 0}, SCH_CNG = {FBQ_CNG = 0}, PCR_QUE_INT01 = {QPCR_INT1 = 0, QPCR_INT0 = 3610}, PCR_QUE_INT23 = {QPCR_INT3 = 61439, QPCR_INT2 = 65501}, RSRVD8 = {32, 4018116456, 0, 66504, 4017950416, 1689, 4018112168, 4018113668, 4018113648, 4018116520}, RSM_CTRL0 = {RSM_ENABLE = 0, RSM_RESET = 0, RSRVD1 = 0, VPI_MASK = 0, RSRVD2 = 0, RSRVD3 = 0, RSM_PHALT = 0, RSRVD4 = 0, FWALL_EN = 0, RSM_FBQ_DIS = 0, RSM_STAT_DIS = 0, GTO_EN = 1, MAX_LEN = 59, GDIS_PRI = 8}, RSM_CTRL1 = {EN_PROG_BLK_SZ = 0, VCI_IT_BLK_SZ = 0, RSRVD1 = 0, RSRVD2 = 0, RSRVD3 = 0, RSRVD4 = 1, OAM_FF_DSC = 0, OAM_EN = 0, OAM_QU_EN = 0, OAM_BFR_QU = 0, OAM_STAT_QU = 0}, RSM_FQBASE = {FBQ1_BASE = 61311, FBQ0_BASE = 38860}, RSM_FQCTRL = {RSRVD1 = 0, FBQ_SIZE = 0, FWD_RND = 0, FBQ0_RTN = 0, FWD_EN = 0, FBQ_UD_INT = 0}, RSM_TBASE = {RSM_VCCB = 61311, RSM_ITB = 38752}, RSM_TO = {RSM_TO_PER = 61311, RSM_TO_CNT = 35516}, RS_QBASE = {RSRVD1 = 15327, RS_SIZE = 3, RS_QBASE = 39924}, RSRVD9 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, CELL_XMIT_CNT = {CELL_XMIT_CNT = 4018116448}, CELL_RCVD_CNT = {CELL_RCVD_CNT = 0}, CELL_DSC_CNT = {CELL_DSC_CNT = 4018117620}, AAL5_DSC_CNT = {RSRVD1 = 0, AAL5_DSC_CNT = 0}, RSRVD10 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, HOST_MBOX = {HOST_MBOX = 0}, HOST_ST_WR = {RSM_HS_WRITE = 0, SEG_HS_WRITE = 0}, RSRVD11 = {0, 4018111652}, LP_MBOX = {LP_MBOX = 0}, RSRVD12 = {562720, 0, 0}, HOST_ISTAT0 = {PFAIL = 0, PHY_INTR = 0, RSRVD1 = 0, HOST_MBOX_ = 0, LP_MBOX_READ = 0, RSRVD2 = 0, RSRVD3 = 0, RSRVD4 = 0, HSTAT1 = 0, RSRVD5 = 0, GFC_LINK = 0, RSM_RUN = 0, RSM_HS_WRITE = 0, RSM_LS_WRITE = 0, RSRVD6 = 0, SEG_RUN = 0, SEG_HS_WRITE = 0, SEG_LS_WRITE = 0, RSRVD7 = 0, AAL5_DSC_RLOVR = 0, CELL_DSC_RLOVR = 0, CELL_RCVD_RLOVR = 0, CELL_XMT_RLOVR = 0}, HOST_ISTAT1 = {PCI_BUS_EROR = 0, RSRVD1 = 0, DMA_AFULL = 0, FR_PAR_ERR = 0, FR_SYNC_ERR = 0, RSRVD2 = 0, RS_QUEUE_FULL = 0, RSM_OVFL = 0, RSM_HS_FULL = 0, RSM_LS_FULL = 0, RSM_HF_EMPT = 0, RSM_LF_EMPT = 0, RSRVD3 = 0, SEG_UNFL = 0, SEG_HS_FULL = 0, SEG_LS_FULL = 0}, RSRVD13 = {0, 0}, HOST_IMASK0 = {EN_PFAIL = 0, EN_PHY_INTR = 0, RSRVD1 = 0, EN_HOST_MBOX_WRITTEN = 0, EN_LP_MBOX_READ = 0, RSRVD2 = 0, RSRVD3 = 0, RSRVD4 = 0, EN_HSTAT1 = 0, RSRVD5 = 0, EN_GFC_LINK = 0, EN_RSM_RUN = 0, EN_RSM_HS_WRITE = 0, EN_RSM_LS_WRITE = 0, RSRVD6 = 0, EN_SEG_RUN = 0, EN_SEG_HS_WRITE = 0, EN_SEG_LS_WRITE = 0, RSRVD7 = 0, EN_AAL5_DSC_RLOVR = 0, EN_CELL_DSC_RLOVR = 0, EN_CELL_RCVD_RLOVR = 0, EN_CELL_XMIT_RLOVR = 0}, HOST_IMASK1 = {EN_PCI_BUS_ERROR = 1, RSRVD1 = 13, EN_DMA_AFULL = 1, EN_FR_PAR_ERR = 1, EN_FR_SYNC_ERR = 1, RSRVD2 = 125, EN_RSQUEUE_FULL = 1, EN_RSM_OVFL = 0, EN_RSM_HS_FULL = 0, EN_RSM_LS_FULL = 0, EN_RSM_HF_EMPT = 0, EN_RSM_LF_EMPT = 0, RSRVD3 = 115, EN_SEG_UNFL = 0, EN_SEG_HS_FULL = 0, EN_SEG_LS_FULL = 0}, RSRVD14 = {4017768144, 4017758844}, LP_ISTAT0 = {RTC_OVFL = 0, ALARM1 = 0, RSRVD1 = 0, LP_MBOX_WRITTEN = 0, HOST_MBOX_READ = 0, RSRVD2 = 0, RSRVD3 = 0, RSRVD4 = 0, LSTAT1"
<- " = 0, RSRVD5 = 0, GFC_LINK = 0, RSM_RUN = 0, RSM_HS_WRITE = 0, RSM_LS_WRITE = 0, RSRVD6 = 0, SEG_RUN = 0, SEG_HS_WRITE = 0, SEG_LS_WRITE = 0, RSRVD7 = 0, AAL5_DSC_RLOVR = 0, CELL_DSC_RLOVR = 0, CELL_RCVD_RLOVR = 0, CELL_XMIT_RLOVR = 0}, LP_ISTAT1 = {PCI_BUS_EROR = 0, RSRVD1 = 0, DMA_AFULL = 0, FR_PAR_ERR = 0, FR_SYNC_ERR = 0, RSRVD2 = 0, RS_QUEUE_FULL = 0, RSM_OVFL = 0, RSM_HS_FULL = 0, RSM_LS_FULL = 0, RSM_HF_EMPT = 0, RSM_LF_EMPT = 0, RSRVD3 = 0, SEG_UNFL = 0, SEG_HS_FULL = 0, SEG_LS_FULL = 0}, RSRVD15 = {4026527280, 66532}, LP_IMASK0 = {EN_RTC_OVFL = 0, EN_ALARM1 = 0, RSRVD1 = 0, EN_LP_MBOX_WRITTEN = 0, EN_HOST_MBOX_READ = 0, RSRVD2 = 0, RSRVD3 = 0, RSRVD4 = 0, EN_LSTAT1 = 0, RSRVD5 = 0, EN_GFC_LINK = 0, EN_RSM_RUN = 0, EN_RSM_HS_WRITE = 0, EN_RSM_LS_WRITE = 0, RSRVD6 = 0, EN_SEG_RUN = 0, EN_SEG_HS_WRITE = 0, EN_SEG_LS_WRITE = 0, RSRVD7 = 0, EN_AAL5_DSC_RLOVR = 0, EN_CELL_DSC_RLOVR = 0, EN_CELL_RCVD_RLOVR = 1, EN_CELL_XMIT_RLOVR = 1}, LP_IMASK1 = {EN_PCI_BUS_ERROR = 1, RSRVD1 = 13, EN_DMA_AFULL = 1, EN_FR_PAR_ERR = 1, EN_FR_SYNC_ERR = 1, RSRVD2 = 255, EN_RSQUEUE_FULL = 1, EN_RSM_OVFL = 1, EN_RSM_HS_FULL = 1, EN_RSM_LS_FULL = 0, EN_RSM_HS_EMPT = 1, EN_RSM_LS_EMPT = 1, RSRVD3 = 82, EN_SEG_UNFL = 1, EN_SEG_HS_FULL = 0, EN_SEG_LS_FULL = 0}, RSRVD16 = {4, 4026527388}}(gdb) "
-> "frame\n"
<- "#0  main () at a.c:8\n"
   "\032\032/home/users/gesquiel/a.c:8:66:beg:0x104a4\n"
   "(gdb) "
-> "display a\n"
<- "1: a = {CLOCK = {CLOCK = 8191}, ALARM1 = {ALARM1 = 0}, RSRVD1 = 0, SYS_STAT = {RSRVD1 = 30655, PCI_BUS_STATUS = 24, RAMMODE = 0, PROCMODE = 1, FRCFG = 0, VERSION = 10, DEVICE = 4}, RSRVD2 = 1, CONFIG0 = {LP_ENABLE = 0, GLOBAL_RESET = 0, PCI_MSTR_RESET = 0, PCI_ERR_RESET = 0, RSRVD1 = 0, PHY2_EN = 0, INT_LBANK = 0, RSRVD2 = 0, PCI_READ_MULTI = 0, PCI_ARB = 0, STATMODE = 2, FR_RMODE = 0, FR_LOOP = 0, UTOPIA_MODE = 0, ENDIAN = 0, LP_BWAIT = 0, MEMCTRL = 0, BANKSIZE = 0, DIVIDER = 0}, RSRVD3 = 4294836223, INT_DELAY = {RSRVD1 = 1961480, TIMER_LOC = 1, EN_TIMER = 0, EN_STAT_CNT = 0, STAT_CNT = 204}, RSRVD4 = {5, 212, 65748, 4017946624, 4026527152, 4017955812, 0, 0, 0, 0, 0, 0, 0, 67192, 66504, 65588, 5, 32, 65536, 4018111652, 1, 131072, 4294836223, 4017117660}, SEG_CTRL = {SEG_ENABLE = 0, SEG_RESET = 0, VBR_OFFSET = 0, SEG_GFC = 0, DBL_SLOT = 0, CBR_TUN = 0, ADV_ABR_TMPLT = 0, RSRVD1 = 0, TX_FIFO_LEN = 0, CLP0_EOM = 0, OAM_STAT_ID = 0, SEG_ST_HALT = 0, SEG_LS_DIS = 0, SEG_HS_DIS = 0, TX_RND = 0, TR_SIZE = 0}, SEG_VBASE = {SEG_SCHB = 0, SEG_VCCB = 0}, SEG_PMBASE = {SEG_BCKB = 0, SEG_PMB = 0}, SEG_TXBASE = {SEG_TXB = 65535, RSRVD1 = 7, XMIT_INTERVAL = 255, TX_EN = 31}, RSRVD5 = {4017946624, 4026531789, 4243, 4243}, SCH_PRI = {QPCR_ENA7 = 0, QPCR_ENA6 = 0, QPCR_ENA5 = 0, QPCR_ENA4 = 0, QPCR_ENA3 = 0, QPCR_ENA2 = 0, QPCR_ENA1 = 0, QPCR_ENA0 = 0, RSRVD1 = 0, TUN_ENA7 = 0, GFC7 = 0, RSRVD2 = 0, TUN_ENA6 = 0, GFC6 = 0, RSRVD3 = 0, TUN_ENA5 = 0, GFC5 = 0, RSRVD4 = 0, TUN_ENA4 = 0, GFC4 = 0, RSRVD5 = 1, TUN_ENA3 = 1, GFC3 = 1, RSRVD6 = 0, TUN_ENA2 = 0, GFC2 = 0, RSRVD7 = 0, TUN_ENA1 = 1, GFC1 = 1, RSRVD8 = 0, TUN_ENA0 = 1, GFC0 = 0}, RSRVD6 = 4026527732, SCH_SIZE = {TBL_SIZE = 0, RSRVD1 = 0, SLOT_PER = 768}, RSRVD7 = 65588, SCH_ABR_MAX = {RSRVD1 = 61439, VCC_MAX = 61084}, SCH_ABR_CON = {ABR_TRM = 61309, ABR_ADTF = 5481}, SCH_ABRBASE = {RSRVD1 = 0, OOR_EN = 0, OOR_INT = 0, SCH_ABRB = 0}, SCH_CNG = {FBQ_CNG = 0}, PCR_QUE_INT01 = {QPCR_INT1 = 0, QPCR_INT0 = 3610}, PCR_QUE_INT23 = {QPCR_INT3 = 61439, QPCR_INT2 = 65501}, RSRVD8 = {32, 4018116456, 0, 66504, 4017950416, 1689, 4018112168, 4018113668, 4018113648, 4018116520}, RSM_CTRL0 = {RSM_ENABLE = 0, RSM_RESET = 0, RSRVD1 = 0, VPI_MASK = 0, RSRVD2 = 0, RSRVD3 = 0, RSM_PHALT = 0, RSRVD4 = 0, FWALL_EN = 0, RSM_FBQ_DIS = 0, RSM_STAT_DIS = 0, GTO_EN = 1, MAX_LEN = 59, GDIS_PRI = 8}, RSM_CTRL1 = {EN_PROG_BLK_SZ = 0, VCI_IT_BLK_SZ = 0, RSRVD1 = 0, RSRVD2 = 0, RSRVD3 = 0, RSRVD4 = 1, OAM_FF_DSC = 0, OAM_EN = 0, OAM_QU_EN = 0, OAM_BFR_QU = 0, OAM_STAT_QU = 0}, RSM_FQBASE = {FBQ1_BASE = 61311, FBQ0_BASE = 38860}, RSM_FQCTRL = {RSRVD1 = 0, FBQ_SIZE = 0, FWD_RND = 0, FBQ0_RTN = 0, FWD_EN = 0, FBQ_UD_INT = 0}, RSM_TBASE = {RSM_VCCB = 61311, RSM_ITB = 38752}, RSM_TO = {RSM_TO_PER = 61311, RSM_TO_CNT = 35516}, RS_QBASE = {RSRVD1 = 15327, RS_SIZE = 3, RS_QBASE = 39924}, RSRVD9 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, CELL_XMIT_CNT = {CELL_XMIT_CNT = 4018116448}, CELL_RCVD_CNT = {CELL_RCVD_CNT = 0}, CELL_DSC_CNT = {CELL_DSC_CNT = 4018117620}, AAL5_DSC_CNT = {RSRVD1 = 0, AAL5_DSC_CNT = 0}, RSRVD10 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, HOST_MBOX = {HOST_MBOX = 0}, HOST_ST_WR = {RSM_HS_WRITE = 0, SEG_HS_WRITE = 0}, RSRVD11 = {0, 4018111652}, LP_MBOX = {LP_MBOX = 0}, RSRVD12 = {562720, 0, 0}, HOST_ISTAT0 = {PFAIL = 0, PHY_INTR = 0, RSRVD1 = 0, HOST_MBOX_ = 0, LP_MBOX_READ = 0, RSRVD2 = 0, RSRVD3 = 0, RSRVD4 = 0, HSTAT1 = 0, RSRVD5 = 0, GFC_LINK = 0, RSM_RUN = 0, RSM_HS_WRITE = 0, RSM_LS_WRITE = 0, RSRVD6 = 0, SEG_RUN = 0, SEG_HS_WRITE = 0, SEG_LS_WRITE = 0, RSRVD7 = 0, AAL5_DSC_RLOVR = 0, CELL_DSC_RLOVR = 0, CELL_RCVD_RLOVR = 0, CELL_XMT_RLOVR = 0}, HOST_ISTAT1 = {PCI_BUS_EROR = 0, RSRVD1 = 0, DMA_AFULL = 0, FR_PAR_ERR = 0, FR_SYNC_ERR = 0, RSRVD2 = 0, RS_QUEUE_FULL = 0, RSM_OVFL = 0, RSM_HS_FULL = 0, RSM_LS_FULL = 0, RSM_HF_EMPT = 0, RSM_LF_EMPT = 0, RSRVD3 = 0, SEG_UNFL = 0, SEG_HS_FULL = 0, SEG_LS_FULL = 0}, RSRVD13 = {0, 0}, HOST_IMASK0 = {EN_PFAIL = 0, EN_PHY_INTR = 0, RSRVD1 = 0, EN_HOST_MBOX_WRITTEN = 0, EN_LP_MBOX_READ = 0, RSRVD2 = 0, RSRVD3 = 0, RSRVD4 = 0, EN_HSTAT1 = 0, RSRVD5 = 0, EN_GFC_LINK = 0, EN_RSM_RUN = 0, EN_RSM_HS_WRITE = 0, EN_RSM_LS_WRITE = 0, RSRVD6 = 0, EN_SEG_RUN = 0, EN_SEG_HS_WRITE = 0, EN_SEG_LS_WRITE = 0, RSRVD7 = 0, EN_AAL5_DSC_RLOVR = 0, EN_CELL_DSC_RLOVR = 0, EN_CELL_RCVD_RLOVR = 0, EN_CELL_XMIT_RLOVR = 0}, HOST_IMASK1 = {EN_PCI_BUS_ERROR = 1, RSRVD1 = 13, EN_DMA_AFULL = 1, EN_FR_PAR_ERR = 1, EN_FR_SYNC_ERR = 1, RSRVD2 = 125, EN_RSQUEUE_FULL = 1, EN_RSM_OVFL = 0, EN_RSM_HS_FULL = 0, EN_RSM_LS_FULL = 0, EN_RSM_HF_EMPT = 0, EN_RSM_LF_EMPT = 0, RSRVD3 = 115, EN_SEG_UNFL = 0, EN_SEG_HS_FULL = 0, EN_SEG_LS_FULL = 0}, RSRVD14 = {4017768144, 4017758844}, LP_ISTAT0 = {RTC_OVFL = 0, ALARM1 = 0, RSRVD1 = 0, LP_MBOX_WRITTEN = 0, HOST_MBOX_READ = 0, RSRVD2 = 0, RSRVD3 = 0, RSRVD4 = 0, LSTAT1 = 0, RSRVD5 = 0, GFC_LINK = 0, RSM_RUN = 0, RSM_HS_WRITE = 0, RSM_LS_WRITE = 0, RSRVD6 = 0, SEG_RUN = 0, SEG_HS_WRITE = 0, SEG_LS_WRITE = 0, RSRVD7 = 0, AAL5_DSC_RLOVR = 0, CELL_DSC_RLOVR = 0, CELL_RCVD_RLOVR = 0, CELL_XMIT_RLOVR = 0}, LP_ISTAT1 = {PCI_BUS_EROR = 0, RSRVD1 = 0, DMA_AFULL = 0, FR_PAR_ERR = 0, FR_SYNC_ERR = 0, RSRVD2 = 0, RS_QUEUE_FULL = 0, RSM_OVFL = 0, RSM_HS_FULL = 0, RSM_LS_FULL = 0, RSM_HF_EMPT = 0, RSM_LF_EMPT = 0, RSRVD3 = 0, SEG_UNFL = 0, SEG_HS_FULL = 0, SEG_LS_FULL = 0}, RSRVD15 = {4026527280, 66532}, LP_IMASK0 = {EN_RTC_OVFL = 0, EN_ALARM1 = 0, RSRVD1 = 0, EN_LP_MBOX_WRITTEN = 0, EN_HOST_MBOX_READ = 0, RSRVD2 = 0, RSRVD3 = 0, RSRVD4 = 0, EN_LSTAT1 = 0, RSRVD5 = 0, EN_GFC_LINK = 0, EN_RSM_RUN = 0, EN_RSM_HS_WRITE = 0, EN_RSM_LS_WRITE = 0, RSRVD6 = 0, EN_SEG_RUN = 0, EN_SEG_HS_WRITE = 0, EN_SEG_LS_WRITE = 0, RSRVD7 = 0, EN_AAL5_DSC_RLOVR = 0, EN_CELL_DSC_RLOVR = 0, EN_CELL_RCVD_RLOVR = 1, EN_CELL_XMIT_RLOVR = 1}, LP_IMASK1 = {EN_PCI_BUS_ERROR = 1, RSRVD1 = 13, EN_DMA_AFULL = 1, EN_FR_PAR_ERR = 1, EN_FR_SYNC_ERR = 1, RSRVD2 = 255, EN_RSQUEUE_FULL = 1, EN_RSM_OVFL = 1, EN_RSM_HS_FULL = 1, EN_RSM_LS_FULL = 0, EN_RSM_HS_EMPT = 1, EN_RSM_LS_EMPT = 1, RSRVD3 = 82, EN_SEG_UNFL = 1, EN_SEG_HS_FULL = 0, EN_SEG_LS_FULL = 0}, RSRVD16 = {4, 4026527388}}\n"
   "(gdb) "
#  Creating display...
#  Creating display...done.
#  Display 1: a (enabled, scope main)
#  Display 1: a (enabled, scope main)
#  In display 1: a (double-click to show more)
#  In display 1: a (double-click to show more)
#  In display 1: a (double-click to hide)
-> "output unsigned\n"
<- "Attempt to use a type name as an expression\n"
   "(gdb) "
#  In display 1: a.SYS_STAT (double-click to hide)
