patch-2.1.73 linux/arch/mips/kernel/r4k_fpu.S
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- Lines: 201
- Date:
Wed Dec 10 10:31:09 1997
- Orig file:
v2.1.72/linux/arch/mips/kernel/r4k_fpu.S
- Orig date:
Mon Jul 7 08:18:53 1997
diff -u --recursive --new-file v2.1.72/linux/arch/mips/kernel/r4k_fpu.S linux/arch/mips/kernel/r4k_fpu.S
@@ -10,7 +10,7 @@
* Multi-arch abstraction and asm macros for easier reading:
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
*
- * $Id: r4k_fpu.S,v 1.2 1997/06/25 16:57:18 ralf Exp $
+ * $Id: r4k_fpu.S,v 1.3 1997/12/01 16:56:06 ralf Exp $
*/
#include <asm/asm.h>
#include <asm/fpregdef.h>
@@ -21,7 +21,7 @@
.set noreorder
.set mips3
/* Save floating point context */
- LEAF(r4k_save_fp_context)
+LEAF(r4k_save_fp_context)
mfc0 t1,CP0_STATUS
sll t2,t1,2
bgez t2,2f
@@ -31,41 +31,41 @@
bgez t2,1f
nop
/* Store the 16 odd double precision registers */
- swc1 $f1,(SC_FPREGS+8)(a0)
- swc1 $f3,(SC_FPREGS+24)(a0)
- swc1 $f5,(SC_FPREGS+40)(a0)
- swc1 $f7,(SC_FPREGS+56)(a0)
- swc1 $f9,(SC_FPREGS+72)(a0)
- swc1 $f11,(SC_FPREGS+88)(a0)
- swc1 $f13,(SC_FPREGS+104)(a0)
- swc1 $f15,(SC_FPREGS+120)(a0)
- swc1 $f17,(SC_FPREGS+136)(a0)
- swc1 $f19,(SC_FPREGS+152)(a0)
- swc1 $f21,(SC_FPREGS+168)(a0)
- swc1 $f23,(SC_FPREGS+184)(a0)
- swc1 $f25,(SC_FPREGS+200)(a0)
- swc1 $f27,(SC_FPREGS+216)(a0)
- swc1 $f29,(SC_FPREGS+232)(a0)
- swc1 $f31,(SC_FPREGS+248)(a0)
+ sdc1 $f1,(SC_FPREGS+8)(a0)
+ sdc1 $f3,(SC_FPREGS+24)(a0)
+ sdc1 $f5,(SC_FPREGS+40)(a0)
+ sdc1 $f7,(SC_FPREGS+56)(a0)
+ sdc1 $f9,(SC_FPREGS+72)(a0)
+ sdc1 $f11,(SC_FPREGS+88)(a0)
+ sdc1 $f13,(SC_FPREGS+104)(a0)
+ sdc1 $f15,(SC_FPREGS+120)(a0)
+ sdc1 $f17,(SC_FPREGS+136)(a0)
+ sdc1 $f19,(SC_FPREGS+152)(a0)
+ sdc1 $f21,(SC_FPREGS+168)(a0)
+ sdc1 $f23,(SC_FPREGS+184)(a0)
+ sdc1 $f25,(SC_FPREGS+200)(a0)
+ sdc1 $f27,(SC_FPREGS+216)(a0)
+ sdc1 $f29,(SC_FPREGS+232)(a0)
+ sdc1 $f31,(SC_FPREGS+248)(a0)
/* Store the 16 even double precision registers */
1:
- swc1 $f0,(SC_FPREGS+0)(a0)
- swc1 $f2,(SC_FPREGS+16)(a0)
- swc1 $f4,(SC_FPREGS+32)(a0)
- swc1 $f6,(SC_FPREGS+48)(a0)
- swc1 $f8,(SC_FPREGS+64)(a0)
- swc1 $f10,(SC_FPREGS+80)(a0)
- swc1 $f12,(SC_FPREGS+96)(a0)
- swc1 $f14,(SC_FPREGS+112)(a0)
- swc1 $f16,(SC_FPREGS+128)(a0)
- swc1 $f18,(SC_FPREGS+144)(a0)
- swc1 $f20,(SC_FPREGS+160)(a0)
- swc1 $f22,(SC_FPREGS+176)(a0)
- swc1 $f24,(SC_FPREGS+192)(a0)
- swc1 $f26,(SC_FPREGS+208)(a0)
- swc1 $f28,(SC_FPREGS+224)(a0)
- swc1 $f30,(SC_FPREGS+240)(a0)
+ sdc1 $f0,(SC_FPREGS+0)(a0)
+ sdc1 $f2,(SC_FPREGS+16)(a0)
+ sdc1 $f4,(SC_FPREGS+32)(a0)
+ sdc1 $f6,(SC_FPREGS+48)(a0)
+ sdc1 $f8,(SC_FPREGS+64)(a0)
+ sdc1 $f10,(SC_FPREGS+80)(a0)
+ sdc1 $f12,(SC_FPREGS+96)(a0)
+ sdc1 $f14,(SC_FPREGS+112)(a0)
+ sdc1 $f16,(SC_FPREGS+128)(a0)
+ sdc1 $f18,(SC_FPREGS+144)(a0)
+ sdc1 $f20,(SC_FPREGS+160)(a0)
+ sdc1 $f22,(SC_FPREGS+176)(a0)
+ sdc1 $f24,(SC_FPREGS+192)(a0)
+ sdc1 $f26,(SC_FPREGS+208)(a0)
+ sdc1 $f28,(SC_FPREGS+224)(a0)
+ sdc1 $f30,(SC_FPREGS+240)(a0)
sw t1,SC_FPC_CSR(a0)
cfc1 t0,$0 # implementation/version
@@ -80,7 +80,8 @@
.set macro
END(r4k_save_fp_context)
-/* Restore fpu state:
+/*
+ * Restore fpu state:
* - fp gp registers
* - cp1 status/control register
*
@@ -88,7 +89,7 @@
* frame on the current content of c0_status, not on the content of the
* stack frame which might have been changed by the user.
*/
- LEAF(r4k_restore_fp_context)
+LEAF(r4k_restore_fp_context)
mfc0 t1,CP0_STATUS
sll t0,t1,2
bgez t0,2f
@@ -99,52 +100,46 @@
/* Restore the 16 odd double precision registers only
* when enabled in the cp0 status register.
*/
- lwc1 $f1,(SC_FPREGS+8)(a0)
- lwc1 $f3,(SC_FPREGS+24)(a0)
- lwc1 $f5,(SC_FPREGS+40)(a0)
- lwc1 $f7,(SC_FPREGS+56)(a0)
- lwc1 $f9,(SC_FPREGS+72)(a0)
- lwc1 $f11,(SC_FPREGS+88)(a0)
- lwc1 $f13,(SC_FPREGS+104)(a0)
- lwc1 $f15,(SC_FPREGS+120)(a0)
- lwc1 $f17,(SC_FPREGS+136)(a0)
- lwc1 $f19,(SC_FPREGS+152)(a0)
- lwc1 $f21,(SC_FPREGS+168)(a0)
- lwc1 $f23,(SC_FPREGS+184)(a0)
- lwc1 $f25,(SC_FPREGS+200)(a0)
- lwc1 $f27,(SC_FPREGS+216)(a0)
- lwc1 $f29,(SC_FPREGS+232)(a0)
- lwc1 $f31,(SC_FPREGS+248)(a0)
+ ldc1 $f1,(SC_FPREGS+8)(a0)
+ ldc1 $f3,(SC_FPREGS+24)(a0)
+ ldc1 $f5,(SC_FPREGS+40)(a0)
+ ldc1 $f7,(SC_FPREGS+56)(a0)
+ ldc1 $f9,(SC_FPREGS+72)(a0)
+ ldc1 $f11,(SC_FPREGS+88)(a0)
+ ldc1 $f13,(SC_FPREGS+104)(a0)
+ ldc1 $f15,(SC_FPREGS+120)(a0)
+ ldc1 $f17,(SC_FPREGS+136)(a0)
+ ldc1 $f19,(SC_FPREGS+152)(a0)
+ ldc1 $f21,(SC_FPREGS+168)(a0)
+ ldc1 $f23,(SC_FPREGS+184)(a0)
+ ldc1 $f25,(SC_FPREGS+200)(a0)
+ ldc1 $f27,(SC_FPREGS+216)(a0)
+ ldc1 $f29,(SC_FPREGS+232)(a0)
+ ldc1 $f31,(SC_FPREGS+248)(a0)
- /* Restore the 16 even double precision registers
+ /*
+ * Restore the 16 even double precision registers
* when cp1 was enabled in the cp0 status register.
*/
-1:
- lwc1 $f0,(SC_FPREGS+0)(a0)
- lwc1 $f2,(SC_FPREGS+16)(a0)
- lwc1 $f4,(SC_FPREGS+32)(a0)
- lwc1 $f6,(SC_FPREGS+48)(a0)
- lwc1 $f8,(SC_FPREGS+64)(a0)
- lwc1 $f10,(SC_FPREGS+80)(a0)
- lwc1 $f12,(SC_FPREGS+96)(a0)
- lwc1 $f14,(SC_FPREGS+112)(a0)
- lwc1 $f16,(SC_FPREGS+128)(a0)
- lwc1 $f18,(SC_FPREGS+144)(a0)
- lwc1 $f20,(SC_FPREGS+160)(a0)
- lwc1 $f22,(SC_FPREGS+176)(a0)
- lwc1 $f24,(SC_FPREGS+192)(a0)
- lwc1 $f26,(SC_FPREGS+208)(a0)
- lwc1 $f28,(SC_FPREGS+224)(a0)
- lwc1 $f30,(SC_FPREGS+240)(a0)
- ctc1 t0,fcr31
-
- jr ra
- .set nomacro
- nop
- .set macro
-2:
+1: ldc1 $f0,(SC_FPREGS+0)(a0)
+ ldc1 $f2,(SC_FPREGS+16)(a0)
+ ldc1 $f4,(SC_FPREGS+32)(a0)
+ ldc1 $f6,(SC_FPREGS+48)(a0)
+ ldc1 $f8,(SC_FPREGS+64)(a0)
+ ldc1 $f10,(SC_FPREGS+80)(a0)
+ ldc1 $f12,(SC_FPREGS+96)(a0)
+ ldc1 $f14,(SC_FPREGS+112)(a0)
+ ldc1 $f16,(SC_FPREGS+128)(a0)
+ ldc1 $f18,(SC_FPREGS+144)(a0)
+ ldc1 $f20,(SC_FPREGS+160)(a0)
+ ldc1 $f22,(SC_FPREGS+176)(a0)
+ ldc1 $f24,(SC_FPREGS+192)(a0)
+ ldc1 $f26,(SC_FPREGS+208)(a0)
+ ldc1 $f28,(SC_FPREGS+224)(a0)
+ ldc1 $f30,(SC_FPREGS+240)(a0)
jr ra
- .set nomacro
+ ctc1 t0,fcr31
+
+2: jr ra
nop
- .set macro
END(r4k_restore_fp_context)
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