patch-2.1.44 linux/include/asm-mips/mipsregs.h
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- Lines: 257
- Date:
Thu Jun 26 12:33:40 1997
- Orig file:
v2.1.43/linux/include/asm-mips/mipsregs.h
- Orig date:
Wed Dec 13 02:39:46 1995
diff -u --recursive --new-file v2.1.43/linux/include/asm-mips/mipsregs.h linux/include/asm-mips/mipsregs.h
@@ -5,17 +5,18 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 1994, 1995 by Ralf Baechle
+ * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ * Modified for further R[236]000 support by Paul M. Antoine, 1996.
*/
-
#ifndef __ASM_MIPS_MIPSREGS_H
#define __ASM_MIPS_MIPSREGS_H
+#include <linux/linkage.h>
+
/*
* The following macros are especially useful for __asm__
* inline assembler.
*/
-
#ifndef __STR
#define __STR(x) #x
#endif
@@ -24,17 +25,6 @@
#endif
/*
- * On the R2000/3000 load instructions are not interlocked -
- * we therefore sometimes need to fill load delay slots with a nop
- * which would be useless for ISA >= 2.
- */
-#if !defined (__R4000__)
-#define FILL_LDS nop
-#else
-#define FILL_LDS
-#endif
-
-/*
* Coprocessor 0 register names
*/
#define CP0_INDEX $0
@@ -67,6 +57,20 @@
#define CP0_ERROREPC $30
/*
+ * R4640/R4650 cp0 register names. These registers are listed
+ * here only for completeness; without MMU these CPUs are not useable
+ * by Linux. A future ELKS port might take make Linux run on them
+ * though ...
+ */
+#define CP0_IBASE $0
+#define CP0_IBOUND $1
+#define CP0_DBASE $2
+#define CP0_DBOUND $3
+#define CP0_CALG $17
+#define CP0_IWATCH $18
+#define CP0_DWATCH $19
+
+/*
* Coprocessor 1 (FPU) register names
*/
#define CP1_REVISION $0
@@ -104,6 +108,9 @@
: "=r" (__res)); \
__res;})
+/*
+ * For now use this only with interrupts disabled!
+ */
#define read_64bit_cp0_register(source) \
({ int __res; \
__asm__ __volatile__( \
@@ -176,9 +183,14 @@
/*
* Inline code for use of the ll and sc instructions
*
- * FIXME: This instruction is only available on MIPS ISA >=3.
+ * FIXME: This instruction is only available on MIPS ISA >=2.
* Since these operations are only being used for atomic operations
* the easiest workaround for the R[23]00 is to disable interrupts.
+ * This fails for R3000 SMP machines which use that many different
+ * technologies as replacement that it is difficult to create even
+ * just a hook for for all machines to hook into. The only good
+ * thing is that there is currently no R3000 SMP machine on the
+ * Linux/MIPS target list ...
*/
#define load_linked(addr) \
({ \
@@ -187,7 +199,7 @@
__asm__ __volatile__( \
"ll\t%0,(%1)" \
: "=r" (__res) \
- : "r" ((unsigned int) (addr))); \
+ : "r" ((unsigned long) (addr))); \
\
__res; \
})
@@ -205,35 +217,53 @@
})
/*
- * Bitfields in the cp0 status register
- *
- * Refer to the MIPS R4xx0 manuals, chapter 5 for explanation.
- * FIXME: This doesn't cover all R4xx0 processors.
+ * Bitfields in the R4xx0 cp0 status register
*/
-#define ST0_IE (1 << 0)
-#define ST0_EXL (1 << 1)
-#define ST0_ERL (1 << 2)
-#define ST0_KSU (3 << 3)
-# define KSU_USER (2 << 3)
-# define KSU_SUPERVISOR (1 << 3)
-# define KSU_KERNEL (0 << 3)
-#define ST0_UX (1 << 5)
-#define ST0_SX (1 << 6)
-#define ST0_KX (1 << 7)
-#define ST0_IM (255 << 8)
-#define ST0_DE (1 << 16)
-#define ST0_CE (1 << 17)
-#define ST0_CH (1 << 18)
-#define ST0_SR (1 << 20)
-#define ST0_BEV (1 << 22)
-#define ST0_RE (1 << 25)
-#define ST0_FR (1 << 26)
-#define ST0_CU (15 << 28)
-#define ST0_CU0 (1 << 28)
-#define ST0_CU1 (1 << 29)
-#define ST0_CU2 (1 << 30)
-#define ST0_CU3 (1 << 31)
-#define ST0_XX (1 << 31) /* R8000/R10000 naming */
+#define ST0_IE 0x00000001
+#define ST0_EXL 0x00000002
+#define ST0_ERL 0x00000004
+#define ST0_KSU 0x00000018
+# define KSU_USER 0x00000010
+# define KSU_SUPERVISOR 0x00000008
+# define KSU_KERNEL 0x00000000
+#define ST0_UX 0x00000020
+#define ST0_SX 0x00000040
+#define ST0_KX 0x00000080
+
+/*
+ * Bitfields in the R[23]000 cp0 status register.
+ */
+#define ST0_KUC 0x00000001
+#define ST0_IEP 0x00000002
+#define ST0_KUP 0x00000004
+#define ST0_IEO 0x00000008
+#define ST0_KUO 0x00000010
+/* bits 6 & 7 are reserved on R[23]000 */
+
+/*
+ * Bits specific to the R4640/R4650
+ */
+#define ST0_UM <1 << 4)
+#define ST0_IL (1 << 23)
+#define ST0_DL (1 << 24)
+
+/*
+ * Status register bits available in all MIPS CPUs.
+ */
+#define ST0_IM 0x0000ff00
+#define ST0_DE 0x00010000
+#define ST0_CE 0x00020000
+#define ST0_CH 0x00040000
+#define ST0_SR 0x00100000
+#define ST0_BEV 0x00400000
+#define ST0_RE 0x02000000
+#define ST0_FR 0x04000000
+#define ST0_CU 0xf0000000
+#define ST0_CU0 0x10000000
+#define ST0_CU1 0x20000000
+#define ST0_CU2 0x40000000
+#define ST0_CU3 0x80000000
+#define ST0_XX 0x80000000 /* MIPS IV naming */
/*
* Bitfields and bit numbers in the coprocessor 0 cause register.
@@ -264,5 +294,78 @@
#define CAUSEF_CE (3 << 28)
#define CAUSEB_BD 31
#define CAUSEF_BD (1 << 31)
+
+/*
+ * Bits in the coprozessor 0 config register.
+ */
+#define CONFIG_DB (1 << 4)
+#define CONFIG_IB (1 << 5)
+#define CONFIG_SC (1 << 17)
+
+/*
+ * R10000 performance counter definitions.
+ *
+ * FIXME: The R10000 performance counter opens a nice way to implement CPU
+ * time accounting with a precission of one cycle. I don't have
+ * R10000 silicon but just a manual, so ...
+ */
+
+/*
+ * Events counted by counter #0
+ */
+#define CE0_CYCLES 0
+#define CE0_INSN_ISSUED 1
+#define CE0_LPSC_ISSUED 2
+#define CE0_S_ISSUED 3
+#define CE0_SC_ISSUED 4
+#define CE0_SC_FAILED 5
+#define CE0_BRANCH_DECODED 6
+#define CE0_QW_WB_SECONDARY 7
+#define CE0_CORRECTED_ECC_ERRORS 8
+#define CE0_ICACHE_MISSES 9
+#define CE0_SCACHE_I_MISSES 10
+#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
+#define CE0_EXT_INTERVENTIONS_REQ 12
+#define CE0_EXT_INVALIDATE_REQ 13
+#define CE0_VIRTUAL_COHERENCY_COND 14
+#define CE0_INSN_GRADUATED 15
+
+/*
+ * Events counted by counter #1
+ */
+#define CE1_CYCLES 0
+#define CE1_INSN_GRADUATED 1
+#define CE1_LPSC_GRADUATED 2
+#define CE1_S_GRADUATED 3
+#define CE1_SC_GRADUATED 4
+#define CE1_FP_INSN_GRADUATED 5
+#define CE1_QW_WB_PRIMARY 6
+#define CE1_TLB_REFILL 7
+#define CE1_BRANCH_MISSPREDICTED 8
+#define CE1_DCACHE_MISS 9
+#define CE1_SCACHE_D_MISSES 10
+#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
+#define CE1_EXT_INTERVENTION_HITS 12
+#define CE1_EXT_INVALIDATE_REQ 13
+#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
+#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
+
+/*
+ * These flags define in which priviledge mode the counters count events
+ */
+#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
+#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
+#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
+#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
+
+#ifndef __LANGUAGE_ASSEMBLY__
+/*
+ * Functions to access the performance counter and control registers
+ */
+extern asmlinkage unsigned int read_perf_cntr(unsigned int counter);
+extern asmlinkage void write_perf_cntr(unsigned int counter, unsigned int val);
+extern asmlinkage unsigned int read_perf_cntl(unsigned int counter);
+extern asmlinkage void write_perf_cntl(unsigned int counter, unsigned int val);
+#endif
#endif /* __ASM_MIPS_MIPSREGS_H */
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