patch-2.1.25 linux/drivers/net/de4x5.c
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- Lines: 4121
- Date:
Sun Feb 2 15:18:37 1997
- Orig file:
v2.1.24/linux/drivers/net/de4x5.c
- Orig date:
Thu Jan 2 15:55:18 1997
diff -u --recursive --new-file v2.1.24/linux/drivers/net/de4x5.c linux/drivers/net/de4x5.c
@@ -1,12 +1,13 @@
-/* de4x5.c: A DIGITAL DE425/DE434/DE435/DE450/DE500 ethernet driver for Linux.
+/* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
+ ethernet driver for Linux.
Copyright 1994, 1995 Digital Equipment Corporation.
This software may be used and distributed according to the terms of
the GNU Public License, incorporated herein by reference.
- This driver is written for the Digital Equipment Corporation series
- of EtherWORKS ethernet cards:
+ Originally, this driver was written for the Digital Equipment
+ Corporation series of EtherWORKS ethernet cards:
DE425 TP/COAX EISA
DE434 TP PCI
@@ -14,6 +15,24 @@
DE450 TP/COAX/AUI PCI
DE500 10/100 PCI Fasternet
+ but it will now attempt to support all cards which conform to the
+ Digital Semiconductor SROM Specification. The driver currently
+ recognises the following chips:
+
+ DC21040 (no SROM)
+ DC21041[A]
+ DC21140[A]
+
+ I plan to add DC2114[23] support ASAP, time permitting. So far the
+ driver is known to work with the following cards:
+
+ KINGSTON
+ Linksys
+ ZNYX342
+ SMC8432
+ SMC9332 (w/new SROM)
+ ZNYX31[45]
+
The driver has been tested on a relatively busy network using the DE425,
DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
16M of data to a DECstation 5000/200 as follows:
@@ -32,9 +51,11 @@
The author may be reached at davies@maniac.ultranet.com.
=========================================================================
- This driver has been written substantially from scratch, although its
+ This driver has been written substantially from scratch, although its
inheritance of style and stack interface from 'ewrk3.c' and in turn from
- Donald Becker's 'lance.c' should be obvious.
+ Donald Becker's 'lance.c' should be obvious. With the module autoload of
+ every usable DECchip board, I pinched Donald's 'next_module' field to
+ link my modules together.
Upto 15 EISA cards can be supported under this driver, limited primarily
by the available IRQ lines. I have checked different configurations of
@@ -46,49 +67,42 @@
to the differences in the EISA and PCI CSR address offsets from the base
address.
- The ability to load this driver as a loadable module has been included
- and used extensively during the driver development (to save those long
- reboot sequences). Loadable module support under PCI and EISA has been
+ The ability to load this driver as a loadable module has been included
+ and used extensively during the driver development (to save those long
+ reboot sequences). Loadable module support under PCI and EISA has been
achieved by letting the driver autoprobe as if it were compiled into the
- kernel, except that there is no autoprobing of the IRQ lines. This is of
- no great consequence except do make sure you're not sharing interrupts
- with anything that cannot accommodate interrupt sharing! By default,
- the driver will autoprobe for the next available card.
-
- Essentially, the I/O address and IRQ information are ignored and filled
- in later by the PCI BIOS during the PCI probe. Note that the board
- should be in the system at boot time so that its I/O address and IRQ are
- allocated by the PCI BIOS automatically.
+ kernel. Do make sure you're not sharing interrupts with anything that
+ cannot accommodate interrupt sharing!
To utilise this ability, you have to do 8 things:
0) have a copy of the loadable modules code installed on your system.
1) copy de4x5.c from the /linux/drivers/net directory to your favourite
temporary directory.
- 2) edit the source code near line 4146 to reflect the I/O address you're
- using (only if you want to manually load the module), or assign these
- when loading by:
+ 2) for fixed autoprobes (not recommended), edit the source code near
+ line 4927 to reflect the I/O address you're using, or assign these when
+ loading by:
- insmod de4x5.o io=0xghh where g = bus number
- hh = device number
+ insmod de4x5 io=0xghh where g = bus number
+ hh = device number
NB: autoprobing for modules is now supported by default. You may just
use:
- insmod de4x5.o
+ insmod de4x5
- to load the next available board. For a specific board, still use
+ to load all available boards. For a specific board, still use
the 'io=?' above.
3) compile de4x5.c, but include -DMODULE in the command line to ensure
that the correct bits are compiled (see end of source code).
4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
kernel with the de4x5 configuration turned off and reboot.
- 5) insmod de4x5.o [io=0xghh]
- 6) run the net startup bits for your new eth?? interface(s) manually
- (usually /etc/rc.inet[12] at boot time).
+ 5) insmod de4x5 [io=0xghh]
+ 6) run the net startup bits for your new eth?? interface(s) manually
+ (usually /etc/rc.inet[12] at boot time).
7) enjoy!
- To unload a module, turn off the associated interface(s)
+ To unload a module, turn off the associated interface(s)
'ifconfig eth?? down' then 'rmmod de4x5'.
Automedia detection is included so that in principal you can disconnect
@@ -99,13 +113,7 @@
By default, the driver will now autodetect any DECchip based card.
Should you have a need to restrict the driver to DIGITAL only cards, you
can compile with a DEC_ONLY define, or if loading as a module, use the
- 'dec_only=1' parameter. However, this "feature" is in no way supported
- nor tested in this driver and the user may use it at his/her sole
- discretion. I have had 2 conflicting reports that my driver will or
- won't work with Znyx. Try Donald Becker's 'tulip.c' if this driver
- doesn't work for you. I will not be supporting Znyx and SMC cards since
- I have no information on them and can't test them in a system (this
- applies most particularly to the DC21140 based cards).
+ 'dec_only=1' parameter.
I've changed the timing routines to use the kernel timer and scheduling
functions so that the hangs and other assorted problems that occurred
@@ -126,6 +134,17 @@
aligned DMA transfers and the Alphas get alignment traps with non
longword aligned data copies (which makes them really slow). No comment.
+ I have added SROM decoding routines to make this driver work with any
+ card that supports the Digital Semiconductor SROM spec. This will help
+ all cards running the dc2114x series chips in particular. Cards using
+ the dc2104x chips should run correctly with the basic driver. I'm in
+ debt to <mjacob@feral.com> for the testing and feedback that helped get
+ this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
+ (with the latest SROM complying with the SROM spec V3: their first was
+ broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
+ (quad 21041 MAC) cards also appear to work despite their incorrectly
+ wired IRQs.
+
TO DO:
------
@@ -134,7 +153,7 @@
----------------
Version Date Description
-
+
0.1 17-Nov-94 Initial writing. ALPHA code release.
0.2 13-Jan-95 Added PCI support for DE435's.
0.21 19-Jan-95 Added auto media detection.
@@ -143,7 +162,7 @@
Add request/release_region code.
Add loadable modules support for PCI.
Clean up loadable modules support.
- 0.23 28-Feb-95 Added DC21041 and DC21140 support.
+ 0.23 28-Feb-95 Added DC21041 and DC21140 support.
Fix missed frame counter value and initialisation.
Fixed EISA probe.
0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
@@ -172,7 +191,7 @@
Add kernel timer code (h/w is too flaky).
Add MII based PHY autosense.
Add new multicasting code.
- Add new autosense algorithms for media/mode
+ Add new autosense algorithms for media/mode
selection using kernel scheduling/timing.
Re-formatted.
Made changes suggested by <jeff@router.patch.net>:
@@ -199,30 +218,40 @@
Add Accton to the list of broken cards.
Fix TX under-run bug for non DC21140 chips.
Fix boot command probe bug in alloc_device() as
- reported by <koen.gadeyne@barco.com> and
+ reported by <koen.gadeyne@barco.com> and
<orava@nether.tky.hut.fi>.
Add cache locks to prevent a race condition as
- reported by <csd@microplex.com> and
+ reported by <csd@microplex.com> and
<baba@beckman.uiuc.edu>.
Upgraded alloc_device() code.
0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
with <csd@microplex.com>
0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
- and <michael@compurex.com>
+ and <michael@compurex.com>.
0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
with a loopback packet.
0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
by <bhat@mundook.cs.mu.OZ.AU>
- 0.45 8-Dec-96 Include endian functions for PPC use, from work
+ 0.45 8-Dec-96 Include endian functions for PPC use, from work
by <cort@cs.nmt.edu>.
0.451 28-Dec-96 Added fix to allow autoprobe for modules after
- suggestion from <mjacob@feral.com>
+ suggestion from <mjacob@feral.com>.
+ 0.5 30-Jan-97 Added SROM decoding functions.
+ Updated debug flags.
+ Fix sleep/wakeup calls for PCI cards, bug reported
+ by <cross@gweep.lkg.dec.com>.
+ Added multi-MAC, one SROM feature from discussion
+ with <mjacob@feral.com>.
+ Added full module autoprobe capability.
+ Added attempt to use an SMC9332 with broken SROM.
+ Added fix for ZYNX multi-mac cards that didn't
+ get their IRQs wired correctly.
=========================================================================
*/
-static const char *version = "de4x5.c:v0.451 96/12/28 davies@maniac.ultranet.com\n";
+static const char *version = "de4x5.c:V0.5 97/1/30 davies@maniac.ultranet.com\n";
#include <linux/module.h>
@@ -280,6 +309,12 @@
int value;
} spd;
int addr; /* MII address for the PHY */
+ u_char *gep; /* Start of GEP sequence block in SROM */
+ u_char *rst; /* Start of reset sequence in SROM */
+ u_int mc; /* Media Capabilities */
+ u_int ana; /* NWay Advertisement */
+ u_int fdx; /* Full DupleX capabilites for each media */
+ u_int ttm; /* Transmit Threshold Mode for each media */
};
#define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
@@ -306,11 +341,23 @@
#define SMC 1
#define ACCTON 2
+/*
+** SROM Repair definitions. If a broken SROM is detected a card may
+** use this information to help figure out what to do. This is a
+** "stab in the dark" and so far for SMC9332's only.
+*/
+static c_char srom_repair_info[][100] = {
+ {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
+ 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
+ 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
+ 0x00,0x18,}
+};
+
#ifdef DE4X5_DEBUG
static int de4x5_debug = DE4X5_DEBUG;
#else
-static int de4x5_debug = 1;
+static int de4x5_debug = (0);
#endif
#ifdef DE4X5_AUTOSENSE /* Should be done on a per adapter basis */
@@ -374,7 +421,7 @@
** Memory Alignment. Each descriptor is 4 longwords long. To force a
** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
** DESC_ALIGN. ALIGN aligns the start address of the private memory area
-** and hence the RX descriptor ring's first entry.
+** and hence the RX descriptor ring's first entry.
*/
#define ALIGN4 ((u_long)4 - 1) /* 1 longword align */
#define ALIGN8 ((u_long)8 - 1) /* 2 longword align */
@@ -455,7 +502,7 @@
char id_block_crc;
char reserved2;
char version;
- char num_adapters;
+ char num_controllers;
char ieee_addr[6];
char info[100];
short chksum;
@@ -500,7 +547,7 @@
int tx_new, tx_old; /* TX descriptor ring pointers */
char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
char frame[64]; /* Min sized packet for loopback*/
- struct enet_statistics stats; /* Public stats */
+ struct net_device_stats stats; /* Public stats */
struct {
u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
u_int unicast;
@@ -518,16 +565,17 @@
char txRingSize;
int bus; /* EISA or PCI */
int bus_num; /* PCI Bus number */
+ int device; /* Device number on PCI bus */
int state; /* Adapter OPENED or CLOSED */
int chipset; /* DC21040, DC21041 or DC21140 */
s32 irq_mask; /* Interrupt Mask (Enable) bits */
s32 irq_en; /* Summary interrupt bits */
int media; /* Media (eg TP), mode (eg 100B)*/
int c_media; /* Remember the last media conn */
+ int fdx; /* media full duplex flag */
int linkOK; /* Link is OK */
int autosense; /* Allow/disallow autosensing */
int tx_enable; /* Enable descriptor polling */
- int lostMedia; /* Possibly lost media */
int setup_f; /* Setup frame filtering type */
int local_state; /* State within a 'media' state */
struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
@@ -543,13 +591,31 @@
s32 csr0; /* Saved Bus Mode Register */
s32 csr6; /* Saved Operating Mode Reg. */
s32 csr7; /* Saved IRQ Mask Register */
+ s32 gep; /* Saved General Purpose Reg. */
+ s32 gepc; /* Control info for GEP */
s32 csr13; /* Saved SIA Connectivity Reg. */
s32 csr14; /* Saved SIA TX/RX Register */
s32 csr15; /* Saved SIA General Register */
int save_cnt; /* Flag if state already saved */
struct sk_buff *skb; /* Save the (re-ordered) skb's */
} cache;
+ struct de4x5_srom srom; /* A copy of the SROM */
+ struct device *next_module; /* Link to the next module */
int rx_ovf; /* Check for 'RX overflow' tag */
+ int useSROM; /* For non-DEC card use SROM */
+ int useMII; /* Infoblock using the MII */
+ int asBitValid; /* Autosense bits in GEP? */
+ int asPolarity; /* 0 => asserted high */
+ int asBit; /* Autosense bit number in GEP */
+ int defMedium; /* SROM default medium */
+ int tcount; /* Last infoblock number */
+ int infoblock_init; /* Initialised this infoblock? */
+ int infoleaf_offset; /* SROM infoleaf for controller */
+ s32 infoblock_csr6; /* csr6 value in SROM infoblock */
+ int infoblock_media; /* infoblock media */
+ int (*infoleaf_fn)(struct device *); /* Pointer to infoleaf function */
+ u_char *rst; /* Pointer to Type 5 reset info */
+ u_char ibn; /* Infoblock number */
};
/*
@@ -564,9 +630,29 @@
int chipset;
struct de4x5_srom srom;
int autosense;
+ int useSROM;
} bus;
/*
+** To get around certain poxy cards that don't provide an SROM
+** for the second and more DECchip, I have to key off the first
+** chip's address. I'll assume there's not a bad SROM iff:
+**
+** o the chipset is the same
+** o the bus number is the same and > 0
+** o the sum of all the returned hw address bytes is 0 or 0x5fa
+**
+** Also have to save the irq for those cards whose hardware designers
+** can't follow the PCI to PCI Bridge Architecture spec.
+*/
+struct {
+ int chipset;
+ int bus;
+ int irq;
+ u_char addr[ETH_ALEN];
+} last = {0,};
+
+/*
** The transmit ring full condition is described by the tx_old and tx_new
** pointers by:
** tx_old = tx_new Empty ring
@@ -586,7 +672,7 @@
static int de4x5_queue_pkt(struct sk_buff *skb, struct device *dev);
static void de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs);
static int de4x5_close(struct device *dev);
-static struct enet_statistics *de4x5_get_stats(struct device *dev);
+static struct net_device_stats *de4x5_get_stats(struct device *dev);
static void de4x5_local_stats(struct device *dev, char *buf, int pkt_len);
static void set_multicast_list(struct device *dev);
static int de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd);
@@ -611,6 +697,7 @@
static int dc21040_autoconf(struct device *dev);
static int dc21041_autoconf(struct device *dev);
static int dc21140m_autoconf(struct device *dev);
+static int srom_autoconf(struct device *dev);
static int de4x5_suspect_state(struct device *dev, int timeout, int prev_state, int (*fn)(struct device *, int), int (*asfn)(struct device *));
static int dc21040_state(struct device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct device *, int));
static int test_media(struct device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
@@ -648,6 +735,10 @@
/*static void srom_busy(u_int command, u_long address);*/
static void sendto_srom(u_int command, u_long addr);
static int getfrom_srom(u_long addr);
+static void srom_map_media(struct device *dev);
+static int srom_infoleaf_info(struct device *dev);
+static void srom_init(struct device *dev);
+static void srom_exec(struct device *dev, u_char *p);
static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
static int mii_rdata(u_long ioaddr);
@@ -661,6 +752,8 @@
static int mii_get_phy(struct device *dev);
static void SetMulticastFilter(struct device *dev);
static int get_hw_addr(struct device *dev);
+static void srom_repair(struct device *dev, int card);
+static int test_bad_enet(struct device *dev, int status);
static void eisa_probe(struct device *dev, u_long iobase);
static void pci_probe(struct device *dev, u_long iobase);
@@ -670,16 +763,29 @@
static char *build_setup_frame(struct device *dev, int mode);
static void disable_ast(struct device *dev);
static void enable_ast(struct device *dev, u32 time_out);
-static long de4x5_switch_to_srl(struct device *dev);
-static long de4x5_switch_to_mii(struct device *dev);
+static long de4x5_switch_mac_port(struct device *dev);
static void timeout(struct device *dev, void (*fn)(u_long data), u_long data, u_long msec);
+static void yawn(struct device *dev, int state);
static int de4x5_dev_index(char *s);
+static void link_modules(struct device *dev, struct device *tmp);
+static struct device *unlink_modules(struct device *p);
static void de4x5_dbg_open(struct device *dev);
static void de4x5_dbg_mii(struct device *dev, int k);
static void de4x5_dbg_media(struct device *dev);
static void de4x5_dbg_srom(struct de4x5_srom *p);
static void de4x5_dbg_rx(struct sk_buff *skb, int len);
static int de4x5_strncmp(char *a, char *b, int n);
+static int dc21041_infoleaf(struct device *dev);
+static int dc21140_infoleaf(struct device *dev);
+static int dc21142_infoleaf(struct device *dev);
+static int dc21143_infoleaf(struct device *dev);
+static int type0_infoblock(struct device *dev, u_char count, u_char *p);
+static int type1_infoblock(struct device *dev, u_char count, u_char *p);
+static int type2_infoblock(struct device *dev, u_char count, u_char *p);
+static int type3_infoblock(struct device *dev, u_char count, u_char *p);
+static int type4_infoblock(struct device *dev, u_char count, u_char *p);
+static int type5_infoblock(struct device *dev, u_char count, u_char *p);
+static int compact_infoblock(struct device *dev, u_char count, u_char *p);
#ifdef MODULE
int init_module(void);
@@ -692,7 +798,37 @@
static char name[DE4X5_NAME_LENGTH + 1];
static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
static int num_de4x5s = 0, num_eth = 0;
-static int cfrv = 0;
+static int cfrv = 0, useSROM = 0;
+
+/*
+** List the SROM infoleaf functions and chipsets
+*/
+struct InfoLeaf {
+ int chipset;
+ int (*fn)(struct device *);
+};
+struct InfoLeaf infoleaf_array[] = {
+ {DC21041, dc21041_infoleaf},
+ {DC21140, dc21140_infoleaf},
+ {DC21142, dc21142_infoleaf},
+ {DC21143, dc21143_infoleaf}
+};
+#define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
+
+/*
+** List the SROM info block functions
+*/
+static int (*dc_infoblock[])(struct device *dev, u_char, u_char *) = {
+ type0_infoblock,
+ type1_infoblock,
+ type2_infoblock,
+ type3_infoblock,
+ type4_infoblock,
+ type5_infoblock,
+ compact_infoblock
+};
+
+#define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
/*
** Miscellaneous defines...
@@ -709,6 +845,13 @@
de4x5_ms_delay(1);\
}
+#define PHY_HARD_RESET {\
+ outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
+ udelay(1000); /* Assert for 1ms */\
+ outl(0x00, DE4X5_GEP);\
+ udelay(2000); /* Wait for 2ms */\
+}
+
/*
** Autoprobing in modules is allowed here. See the top of the file for
@@ -718,23 +861,18 @@
int
de4x5_probe(struct device *dev)
{
- int tmp = num_de4x5s, status = -ENODEV;
+ int status = -ENODEV;
u_long iobase = dev->base_addr;
eisa_probe(dev, iobase);
pci_probe(dev, iobase);
-
- if ((tmp == num_de4x5s) && (iobase != 0) && loading_module) {
- printk("%s: de4x5_probe() cannot find device at 0x%04lx.\n", dev->name,
- iobase);
- }
-
+
/*
** Walk the device list to check that at least one device
** initialised OK
*/
for (; (dev->priv == NULL) && (dev->next != NULL); dev = dev->next);
-
+
if (dev->priv) status = 0;
if (iobase == 0) autoprobed = 1;
@@ -745,70 +883,70 @@
de4x5_hw_init(struct device *dev, u_long iobase)
{
struct bus_type *lp = &bus;
- int tmpbus, tmpchs, status=0;
- int i, media = *((char *)&(lp->srom) + *((char *)&(lp->srom) + 19) * 3);
+ int i, status=0;
char *tmp;
-
+
/* Ensure we're not sleeping */
- if (lp->chipset == DC21041) {
- outl(0, PCI_CFDA);
- de4x5_ms_delay(10);
+ if (lp->bus == EISA) {
+ outb(WAKEUP, PCI_CFPM);
+ } else {
+ pcibios_write_config_byte(lp->bus_num, lp->device << 3,
+ PCI_CFDA_PSM, WAKEUP);
}
-
+ de4x5_ms_delay(10);
+
RESET_DE4X5;
-
+
if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
return -ENXIO; /* Hardware could not reset */
}
-
- /*
+
+ /*
** Now find out what kind of DC21040/DC21041/DC21140 board we have.
*/
+ useSROM = FALSE;
if (lp->bus == PCI) {
PCI_signature(name, lp);
} else {
EISA_signature(name, EISA_ID0);
}
-
+
if (*name == '\0') { /* Not found a board signature */
return -ENXIO;
}
-
+
dev->base_addr = iobase;
if (lp->bus == EISA) {
- printk("%s: %s at 0x%04lx (EISA slot %ld)",
+ printk("%s: %s at 0x%04lx (EISA slot %ld)",
dev->name, name, iobase, ((iobase>>12)&0x0f));
} else { /* PCI port address */
printk("%s: %s at 0x%04lx (PCI bus %d, device %d)", dev->name, name,
iobase, lp->bus_num, lp->device);
}
-
+
printk(", h/w address ");
status = get_hw_addr(dev);
for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
printk("%2.2x:", dev->dev_addr[i]);
}
printk("%2.2x,\n", dev->dev_addr[i]);
-
- tmpbus = lp->bus;
- tmpchs = lp->chipset;
-
+
if (status != 0) {
printk(" which has an Ethernet PROM CRC error.\n");
return -ENXIO;
} else {
struct de4x5_private *lp;
-
- /*
+
+ /*
** Reserve a section of kernel memory for the adapter
** private area and the TX/RX descriptor rings.
*/
- dev->priv = (void *) kmalloc(sizeof(struct de4x5_private) + ALIGN,
+ dev->priv = (void *) kmalloc(sizeof(struct de4x5_private) + ALIGN,
GFP_KERNEL);
if (dev->priv == NULL) {
return -ENOMEM;
}
-
+
/*
** Align to a longword boundary
*/
@@ -816,26 +954,20 @@
dev->priv = (void *)(((u_long)dev->priv + ALIGN) & ~ALIGN);
lp = (struct de4x5_private *)dev->priv;
memset(dev->priv, 0, sizeof(struct de4x5_private));
- lp->bus = tmpbus;
- lp->chipset = tmpchs;
+ lp->bus = bus.bus;
+ lp->bus_num = bus.bus_num;
+ lp->device = bus.device;
+ lp->chipset = bus.chipset;
lp->cache.priv = tmp;
-
- /*
- ** Check for an MII interface
- */
- if (media & MEDIA_MII) { /* MII interface? */
- if (!mii_get_phy(dev)) {
- printk("%s: MII search failed, no device found when one was expected\n", dev->name);
- return -ENXIO;
- }
- } else {
- mii_get_phy(dev); /* Search the MII anyway! */
- }
+ lp->cache.gepc = GEP_INIT;
+ lp->timeout = -1;
+ lp->useSROM = useSROM;
+ memcpy((char *)&lp->srom,(char *)&bus.srom,sizeof(struct de4x5_srom));
/*
** Choose correct autosensing in case someone messed up
*/
- if (de4x5_autosense & AUTO) {
+ if ((de4x5_autosense & AUTO) || lp->useSROM) {
lp->autosense = AUTO;
} else {
if (lp->chipset != DC21140) {
@@ -850,12 +982,12 @@
lp->autosense = de4x5_autosense & 0x00c0;
}
}
-
+ lp->fdx = de4x5_full_duplex;
sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
-
+
/*
** Set up the RX descriptor ring (Intels)
- ** Allocate contiguous receive buffers, long word aligned (Alphas)
+ ** Allocate contiguous receive buffers, long word aligned (Alphas)
*/
#if !defined(__alpha__) && !defined(__powerpc__) && !defined(DE4X5_DO_MEMCPY)
for (i=0; i<NUM_RX_DESC; i++) {
@@ -867,7 +999,7 @@
}
#else
- if ((tmp = (void *)kmalloc(RX_BUFF_SZ * NUM_RX_DESC + ALIGN,
+ if ((tmp = (void *)kmalloc(RX_BUFF_SZ * NUM_RX_DESC + ALIGN,
GFP_KERNEL)) == NULL) {
kfree(lp->cache.priv);
return -ENOMEM;
@@ -885,22 +1017,22 @@
#endif
barrier();
-
+
request_region(iobase, (lp->bus == PCI ? DE4X5_PCI_TOTAL_SIZE :
- DE4X5_EISA_TOTAL_SIZE),
+ DE4X5_EISA_TOTAL_SIZE),
lp->adapter_name);
-
+
lp->rxRingSize = NUM_RX_DESC;
lp->txRingSize = NUM_TX_DESC;
-
+
/* Write the end of list marker to the descriptor lists */
lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
-
+
/* Tell the adapter where the TX/RX rings are located. */
outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
-
+
/* Initialise the IRQ mask and Enable/Disable */
lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
lp->irq_en = IMR_NIM | IMR_AIM;
@@ -909,23 +1041,40 @@
create_packet(dev, lp->frame, sizeof(lp->frame));
/* Check if the RX overflow bug needs testing for */
- tmpchs = cfrv & 0x000000fe;
- if ((lp->chipset == DC21140) && (tmpchs == 0x20)) {
+ i = cfrv & 0x000000fe;
+ if ((lp->chipset == DC21140) && (i == 0x20)) {
lp->rx_ovf = 1;
}
- /* Initialise the adapter state */
+ /* Initialise the SROM pointers if possible */
+ if (lp->useSROM) {
+ lp->state = INITIALISED;
+ de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
+ if (srom_infoleaf_info(dev)) {
+ return -ENXIO;
+ }
+ srom_init(dev);
+ }
+
lp->state = CLOSED;
+ /*
+ ** Check for an MII interface
+ */
+ if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
+ mii_get_phy(dev);
+ }
+
printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
+ printk("INFOLEAF_SIZE: %d\nCOMPACT: %d\n", INFOLEAF_SIZE, COMPACT);
}
-
- if (de4x5_debug > 1) {
+
+ if (de4x5_debug & DEBUG_VERSION) {
printk(version);
}
-
+
/* The DE4X5-specific entries in the device structure. */
dev->open = &de4x5_open;
dev->hard_start_xmit = &de4x5_queue_pkt;
@@ -933,18 +1082,15 @@
dev->get_stats = &de4x5_get_stats;
dev->set_multicast_list = &set_multicast_list;
dev->do_ioctl = &de4x5_ioctl;
-
+
dev->mem_start = 0;
-
- /* Fill in the generic field of the device structure. */
+
+ /* Fill in the generic fields of the device structure. */
ether_setup(dev);
-
+
/* Let the adapter sleep to save power */
- if (lp->chipset == DC21041) {
- outl(0, DE4X5_SICR);
- outl(CFDA_PSM, PCI_CFDA);
- }
-
+ yawn(dev, SLEEP);
+
return status;
}
@@ -956,7 +1102,7 @@
u_long iobase = dev->base_addr;
int i, status = 0;
s32 omr;
-
+
/* Allocate the RX buffers */
for (i=0; i<lp->rxRingSize; i++) {
if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
@@ -968,35 +1114,32 @@
/*
** Wake up the adapter
*/
- if (lp->chipset == DC21041) {
- outl(0, PCI_CFDA);
- de4x5_ms_delay(10);
- }
+ yawn(dev, WAKEUP);
- /*
- ** Re-initialize the DE4X5...
+ /*
+ ** Re-initialize the DE4X5...
*/
status = de4x5_init(dev);
-
+
lp->state = OPEN;
de4x5_dbg_open(dev);
-
- if (request_irq(dev->irq, (void *)de4x5_interrupt, SA_SHIRQ,
+
+ if (request_irq(dev->irq, (void *)de4x5_interrupt, SA_SHIRQ,
lp->adapter_name, dev)) {
printk("de4x5_open(): Requested IRQ%d is busy\n",dev->irq);
status = -EAGAIN;
} else {
- dev->tbusy = 0;
+ dev->tbusy = 0;
dev->start = 1;
dev->interrupt = UNMASK_INTERRUPTS;
dev->trans_start = jiffies;
-
+
START_DE4X5;
-
+
de4x5_setup_intr(dev);
}
-
- if (de4x5_debug > 1) {
+
+ if (de4x5_debug & DEBUG_OPEN) {
printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
@@ -1006,9 +1149,9 @@
printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
}
-
+
MOD_INC_USE_COUNT;
-
+
return status;
}
@@ -1022,15 +1165,15 @@
*/
static int
de4x5_init(struct device *dev)
-{
+{
/* Lock out other processes whilst setting up the hardware */
set_bit(0, (void *)&dev->tbusy);
-
+
de4x5_sw_reset(dev);
-
+
/* Autoconfigure the connected port */
autoconf_media(dev);
-
+
return 0;
}
@@ -1041,22 +1184,25 @@
u_long iobase = dev->base_addr;
int i, j, status = 0;
s32 bmr, omr;
-
+
/* Select the MII or SRL port now and RESET the MAC */
- if (lp->phy[lp->active].id == 0) {
- de4x5_switch_to_srl(dev);
- } else {
- de4x5_switch_to_mii(dev);
+ if (!lp->useSROM) {
+ if (lp->phy[lp->active].id != 0) {
+ lp->infoblock_csr6 = OMR_PS | OMR_HBD;
+ } else {
+ lp->infoblock_csr6 = OMR_TTM;
+ }
+ de4x5_switch_mac_port(dev);
}
- /*
+ /*
** Set the programmable burst length to 8 longwords for all the DC21140
** Fasternet chips and 4 longwords for all others: DMA errors result
** without these values. Cache align 16 long.
*/
bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | CACHE_ALIGN;
outl(bmr, DE4X5_BMR);
-
+
omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
if (lp->chipset == DC21140) {
omr |= (OMR_SDP | OMR_SB);
@@ -1064,26 +1210,26 @@
lp->setup_f = PERFECT;
outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
-
+
lp->rx_new = lp->rx_old = 0;
lp->tx_new = lp->tx_old = 0;
-
+
for (i = 0; i < lp->rxRingSize; i++) {
lp->rx_ring[i].status = cpu_to_le32(R_OWN);
}
-
+
for (i = 0; i < lp->txRingSize; i++) {
lp->tx_ring[i].status = cpu_to_le32(0);
}
-
+
barrier();
-
+
/* Build the setup frame depending on filtering mode */
SetMulticastFilter(dev);
-
+
load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, NULL);
outl(omr|OMR_ST, DE4X5_OMR);
-
+
/* Poll for setup frame completion (adapter interrupts are disabled now) */
sti(); /* Ensure timer interrupts */
for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
@@ -1091,20 +1237,20 @@
if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
}
outl(omr, DE4X5_OMR); /* Stop everything! */
-
+
if (j == 0) {
- printk("%s: Setup frame timed out, status %08x\n", dev->name,
+ printk("%s: Setup frame timed out, status %08x\n", dev->name,
inl(DE4X5_STS));
status = -EIO;
}
-
+
lp->tx_new = (++lp->tx_new) % lp->txRingSize;
lp->tx_old = lp->tx_new;
-
+
return status;
}
-/*
+/*
** Writes a socket buffer address to the next available transmit descriptor
*/
static int
@@ -1121,9 +1267,9 @@
set_bit(0, (void*)&dev->tbusy); /* Stop send re-tries */
if (lp->tx_enable == NO) { /* Cannot send for now */
- return -1;
+ return -1;
}
-
+
/*
** Clean out the TX ring asynchronously to interrupts - sometimes the
** interrupts are lost by delayed descriptor status updates relative to
@@ -1143,8 +1289,8 @@
} else {
de4x5_put_cache(dev, skb);
}
- if (de4x5_debug > 1) {
- printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%ld\n lostMedia:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), dev->tbusy, lp->lostMedia, inl(DE4X5_IMR), inl(DE4X5_OMR), (lp->tx_skb[lp->tx_new] ? "YES" : "NO"));
+ if (de4x5_debug & DEBUG_TX) {
+ printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%ld\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), dev->tbusy, inl(DE4X5_IMR), inl(DE4X5_OMR), (lp->tx_skb[lp->tx_new] ? "YES" : "NO"));
}
} else if (skb->len > 0) {
/* If we already have stuff queued locally, use that first */
@@ -1158,10 +1304,10 @@
set_bit(0, (void*)&dev->tbusy);
load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
-
+
lp->tx_new = (++lp->tx_new) % lp->txRingSize;
dev->trans_start = jiffies;
-
+
if (TX_BUFFS_AVAIL) {
dev->tbusy = 0; /* Another pkt may be queued */
}
@@ -1170,15 +1316,15 @@
}
if (skb) de4x5_putb_cache(dev, skb);
}
-
+
lp->cache.lock = 0;
return status;
}
/*
-** The DE4X5 interrupt handler.
-**
+** The DE4X5 interrupt handler.
+**
** I/O Read/Writes through intermediate PCI bridges are never 'posted',
** so that the asserted interrupt always has some real data to work with -
** if these I/O accesses are ever changed to memory accesses, ensure the
@@ -1194,41 +1340,40 @@
struct de4x5_private *lp;
s32 imr, omr, sts, limit;
u_long iobase;
-
+
if (dev == NULL) {
printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
return;
}
lp = (struct de4x5_private *)dev->priv;
iobase = dev->base_addr;
-
+
if (dev->interrupt)
printk("%s: Re-entering the interrupt handler.\n", dev->name);
-
+
DISABLE_IRQs; /* Ensure non re-entrancy */
dev->interrupt = MASK_INTERRUPTS;
-
+
for (limit=0; limit<8; limit++) {
sts = inl(DE4X5_STS); /* Read IRQ status */
outl(sts, DE4X5_STS); /* Reset the board interrupts */
-
+
if (!(sts & lp->irq_mask)) break;/* All done */
-
+
if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
de4x5_rx(dev);
-
+
if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
- de4x5_tx(dev);
-
+ de4x5_tx(dev);
+
if (sts & STS_LNF) { /* TP Link has failed */
- lp->lostMedia = LOST_MEDIA_THRESHOLD + 1;
lp->irq_mask &= ~IMR_LFM;
}
-
+
if (sts & STS_UNF) { /* Transmit underrun */
de4x5_txur(dev);
}
-
+
if (sts & STS_SE) { /* Bus Error */
STOP_DE4X5;
printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
@@ -1247,7 +1392,7 @@
dev->interrupt = UNMASK_INTERRUPTS;
ENABLE_IRQs;
-
+
return;
}
@@ -1258,11 +1403,11 @@
u_long iobase = dev->base_addr;
int entry;
s32 status;
-
+
for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
entry=lp->rx_new) {
status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
-
+
if (lp->rx_ovf) {
if (inl(DE4X5_MFC) & MFC_FOCM) {
de4x5_rx_ovfc(dev);
@@ -1273,9 +1418,9 @@
if (status & RD_FS) { /* Remember the start of frame */
lp->rx_old = entry;
}
-
+
if (status & RD_LS) { /* Valid frame status */
- lp->linkOK++;
+ if (lp->tx_enable) lp->linkOK++;
if (status & RD_ES) { /* There was an error. */
lp->stats.rx_errors++; /* Update the error stats. */
if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
@@ -1290,9 +1435,9 @@
struct sk_buff *skb;
short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
>> 16) - 4;
-
+
if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
- printk("%s: Insufficient memory; nuking packet.\n",
+ printk("%s: Insufficient memory; nuking packet.\n",
dev->name);
lp->stats.rx_dropped++; /* Really, deferred. */
break;
@@ -1302,12 +1447,12 @@
/* Push up the protocol stack */
skb->protocol=eth_type_trans(skb,dev);
netif_rx(skb);
-
+
/* Update stats */
lp->stats.rx_packets++;
de4x5_local_stats(dev, skb->data, pkt_len);
}
-
+
/* Change buffer ownership for this frame, back to the adapter */
for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
@@ -1316,13 +1461,13 @@
lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
barrier();
}
-
+
/*
** Update entry information
*/
lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
}
-
+
return 0;
}
@@ -1336,33 +1481,29 @@
u_long iobase = dev->base_addr;
int entry;
s32 status;
-
+
for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
if (status < 0) { /* Buffer not sent yet */
break;
} else if (status != 0x7fffffff) { /* Not setup frame */
if (status & TD_ES) { /* An error happened */
- lp->stats.tx_errors++;
+ lp->stats.tx_errors++;
if (status & TD_NC) lp->stats.tx_carrier_errors++;
if (status & TD_LC) lp->stats.tx_window_errors++;
if (status & TD_UF) lp->stats.tx_fifo_errors++;
if (status & TD_EC) lp->pktStats.excessive_collisions++;
if (status & TD_DE) lp->stats.tx_aborted_errors++;
-
- if (status & (TD_LO | TD_NC | TD_EC | TD_LF)) {
- lp->lostMedia++;
- }
+
if (TX_PKT_PENDING) {
outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
}
} else { /* Packet sent */
lp->stats.tx_packets++;
- lp->lostMedia = 0; /* Remove transient problem */
- lp->linkOK++;
+ if (lp->tx_enable) lp->linkOK++;
}
/* Update the collision counter */
- lp->stats.collisions += ((status & TD_EC) ? 16 :
+ lp->stats.collisions += ((status & TD_EC) ? 16 :
((status & TD_CC) >> 3));
/* Free the buffer. */
@@ -1371,7 +1512,7 @@
lp->tx_skb[entry] = NULL;
}
}
-
+
/* Update all the pointers */
lp->tx_old = (++lp->tx_old) % lp->txRingSize;
}
@@ -1380,7 +1521,7 @@
dev->tbusy = 0; /* Clear TX busy flag */
if (dev->interrupt) mark_bh(NET_BH);
}
-
+
return 0;
}
@@ -1389,10 +1530,12 @@
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
int next_tick = DE4X5_AUTOSENSE_MS;
-
+
disable_ast(dev);
-
- if (lp->chipset == DC21140) {
+
+ if (lp->useSROM) {
+ next_tick = srom_autoconf(dev);
+ } else if (lp->chipset == DC21140) {
next_tick = dc21140m_autoconf(dev);
} else if (lp->chipset == DC21041) {
next_tick = dc21041_autoconf(dev);
@@ -1401,7 +1544,7 @@
}
lp->linkOK = 0;
enable_ast(dev, next_tick);
-
+
return 0;
}
@@ -1424,11 +1567,11 @@
}
outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
}
-
+
return 0;
}
-static int
+static int
de4x5_rx_ovfc(struct device *dev)
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
@@ -1445,7 +1588,7 @@
}
outl(omr, DE4X5_OMR);
-
+
return 0;
}
@@ -1455,22 +1598,22 @@
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
u_long iobase = dev->base_addr;
s32 imr, omr;
-
+
disable_ast(dev);
dev->start = 0;
dev->tbusy = 1;
-
- if (de4x5_debug > 1) {
+
+ if (de4x5_debug & DEBUG_CLOSE) {
printk("%s: Shutting down ethercard, status was %8.8x.\n",
dev->name, inl(DE4X5_STS));
}
-
- /*
+
+ /*
** We stop the DE4X5 here... mask interrupts and stop TX & RX
*/
DISABLE_IRQs;
STOP_DE4X5;
-
+
/* Free the associated irq */
free_irq(dev->irq, dev);
lp->state = CLOSED;
@@ -1478,26 +1621,22 @@
/* Free any socket buffers */
de4x5_free_rx_buffs(dev);
de4x5_free_tx_buffs(dev);
-
+
MOD_DEC_USE_COUNT;
-
+
/* Put the adapter to sleep to save power */
- if (lp->chipset == DC21041) {
- outl(0, DE4X5_SICR);
- outl(CFDA_PSM, PCI_CFDA);
- }
-
+ yawn(dev, SLEEP);
+
return 0;
}
-static struct enet_statistics *
-de4x5_get_stats(struct device *dev)
+static struct net_device_stats *de4x5_get_stats(struct device *dev)
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
u_long iobase = dev->base_addr;
-
+
lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
-
+
return &lp->stats;
}
@@ -1523,7 +1662,7 @@
(*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
lp->pktStats.unicast++;
}
-
+
lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
if (lp->pktStats.bins[0] == 0) { /* Reset counters */
memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
@@ -1536,7 +1675,7 @@
load_packet(struct device *dev, char *buf, u32 flags, struct sk_buff *skb)
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
-
+
lp->tx_ring[lp->tx_new].buf = cpu_to_le32(virt_to_bus(buf));
lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
@@ -1544,7 +1683,7 @@
barrier();
lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
barrier();
-
+
return;
}
@@ -1564,17 +1703,17 @@
omr = inl(DE4X5_OMR);
omr |= OMR_PR;
outl(omr, DE4X5_OMR);
- } else {
+ } else {
SetMulticastFilter(dev);
- load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
+ load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
SETUP_FRAME_LEN, NULL);
-
+
lp->tx_new = (++lp->tx_new) % lp->txRingSize;
outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
dev->trans_start = jiffies;
}
}
-
+
return;
}
@@ -1598,26 +1737,26 @@
omr = inl(DE4X5_OMR);
omr &= ~(OMR_PR | OMR_PM);
pa = build_setup_frame(dev, ALL); /* Build the basic frame */
-
+
if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
omr |= OMR_PM; /* Pass all multicasts */
} else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
addrs=dmi->dmi_addr;
dmi=dmi->next;
- if ((*addrs & 0x01) == 1) { /* multicast address? */
+ if ((*addrs & 0x01) == 1) { /* multicast address? */
crc = 0xffffffff; /* init CRC for each address */
for (byte=0;byte<ETH_ALEN;byte++) {/* for each address byte */
- /* process each address bit */
+ /* process each address bit */
for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
}
}
hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
-
+
byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
-
+
byte <<= 1; /* calc offset into setup frame */
if (byte & 0x02) {
byte -= 1;
@@ -1629,14 +1768,14 @@
for (j=0; j<dev->mc_count; j++) {
addrs=dmi->dmi_addr;
dmi=dmi->next;
- for (i=0; i<ETH_ALEN; i++) {
+ for (i=0; i<ETH_ALEN; i++) {
*(pa + (i&1)) = *addrs++;
if (i & 0x01) pa += 4;
}
}
}
outl(omr, DE4X5_OMR);
-
+
return;
}
@@ -1647,18 +1786,18 @@
static void
eisa_probe(struct device *dev, u_long ioaddr)
{
- int i, maxSlots, status;
- u_short vendor, device;
- s32 cfid;
+ int i, maxSlots, status, device;
+ u_short vendor;
+ u32 cfid;
u_long iobase;
struct bus_type *lp = &bus;
char name[DE4X5_STRLEN];
struct device *tmp;
-
- if (!ioaddr && autoprobed) return; /* Been here before ! */
-
+
+ if (autoprobed) return; /* Been here before ! */
+
lp->bus = EISA;
-
+
if (ioaddr == 0) { /* Autoprobing */
iobase = EISA_SLOT_INC; /* Get the first slot address */
i = 1;
@@ -1668,31 +1807,33 @@
i = (ioaddr >> 12);
maxSlots = i + 1;
}
-
- for (status = -ENODEV;
- (i<maxSlots) && (dev!=NULL) && (!loading_module || (num_de4x5s == 0));
- i++, iobase+=EISA_SLOT_INC) {
+
+ for (status= -ENODEV;(i<maxSlots)&&(dev!=NULL);i++,iobase+=EISA_SLOT_INC) {
if (EISA_signature(name, EISA_ID)) {
- cfid = inl(PCI_CFID);
- cfrv = inl(PCI_CFRV);
- device = (u_short)(cfid >> 16);
+ cfid = (u32) inl(PCI_CFID);
+ cfrv = (u_short) inl(PCI_CFRV);
+ device = (cfid >> 8) & 0x00ffff00;
vendor = (u_short) cfid;
-
+
/* Read the EISA Configuration Registers */
dev->irq = inb(EISA_REG0);
dev->irq = de4x5_irq[(dev->irq >> 1) & 0x03];
+ if (is_DC2114x) device |= (cfrv & 0x00f0);
lp->chipset = device;
DevicePresent(DE4X5_APROM);
/* Write the PCI Configuration Registers */
outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
outl(0x00006000, PCI_CFLT);
outl(iobase, PCI_CBIO);
-
+
if (check_region(iobase, DE4X5_EISA_TOTAL_SIZE) == 0) {
if ((tmp = alloc_device(dev, iobase)) != NULL) {
if ((status = de4x5_hw_init(tmp, iobase)) == 0) {
num_de4x5s++;
+ if (loading_module) link_modules(dev, tmp);
+ } else if (loading_module && (tmp != dev)) {
+ kfree(tmp);
}
}
} else if (autoprobed) {
@@ -1700,7 +1841,7 @@
}
}
}
-
+
return;
}
@@ -1724,18 +1865,18 @@
{
u_char irq;
u_char pb, pbus, dev_num, dnum, dev_fn;
- u_short vendor, device, index, status;
+ u_short vendor, index, status;
u_int class = DE4X5_CLASS_CODE;
- u_int iobase;
+ u_int device, iobase;
struct bus_type *lp = &bus;
struct device *tmp;
- if ((!ioaddr || !loading_module) && autoprobed) return;
-
+ if (autoprobed) return;
+
if (!pcibios_present()) return; /* No PCI bus in this machine! */
-
+
lp->bus = PCI;
-
+
if ((ioaddr < 0x1000) && loading_module) {
pbus = (u_short)(ioaddr >> 8);
dnum = (u_short)(ioaddr & 0xff);
@@ -1744,26 +1885,35 @@
dnum = 0;
}
- for (index=0;
- (pcibios_find_class(class, index, &pb, &dev_fn)!= PCIBIOS_DEVICE_NOT_FOUND) &&
- (!loading_module || (num_de4x5s == 0));
+ for (index=0;
+ (pcibios_find_class(class, index, &pb, &dev_fn)!= PCIBIOS_DEVICE_NOT_FOUND);
index++) {
dev_num = PCI_SLOT(dev_fn);
if ((!pbus && !dnum) || ((pbus == pb) && (dnum == dev_num))) {
+ device = 0;
pcibios_read_config_word(pb, PCI_DEVICE, PCI_VENDOR_ID, &vendor);
- pcibios_read_config_word(pb, PCI_DEVICE, PCI_DEVICE_ID, &device);
- if (!(is_DC21040 || is_DC21041 || is_DC21140)) continue;
+ pcibios_read_config_word(pb, PCI_DEVICE, PCI_DEVICE_ID, (u_short *)&device);
+ device <<= 8;
+ if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) {
+ continue;
+ }
+
+ /* Get the chip configuration revision register */
+ pcibios_read_config_dword(pb, PCI_DEVICE, PCI_REVISION_ID, &cfrv);
/* Set the device number information */
lp->device = dev_num;
lp->bus_num = pb;
-
+
/* Set the chipset information */
+ if (is_DC2114x) device |= (cfrv & 0x00f0);
lp->chipset = device;
- /* Get the chip configuration revision register */
- pcibios_read_config_dword(pb, PCI_DEVICE, PCI_REVISION_ID, &cfrv);
+ if (is_DC21142 || is_DC21143) {
+ printk("de4x5: Detected a %s chip. Currently this is unsupported in this driver.\nPlease email the author to request its inclusion!\n", (is_DC21142?"DC21142":"DC21143"));
+ continue;
+ }
/* Get the board I/O address */
pcibios_read_config_dword(pb, PCI_DEVICE, PCI_BASE_ADDRESS_0, &iobase);
@@ -1772,7 +1922,7 @@
/* Fetch the IRQ to be used */
pcibios_read_config_byte(pb, PCI_DEVICE, PCI_INTERRUPT_LINE, &irq);
if ((irq == 0) || (irq == (u_char) 0xff)) continue;
-
+
/* Check if I/O accesses and Bus Mastering are enabled */
pcibios_read_config_word(pb, PCI_DEVICE, PCI_COMMAND, &status);
if (!(status & PCI_COMMAND_IO)) continue;
@@ -1789,15 +1939,18 @@
tmp->irq = irq;
if ((status = de4x5_hw_init(tmp, iobase)) == 0) {
num_de4x5s++;
+ if (loading_module) link_modules(dev, tmp);
+ } else if (loading_module && (tmp != dev)) {
+ kfree(tmp);
}
}
} else if (autoprobed) {
- printk("%s: region already allocated at 0x%04x.\n", dev->name,
+ printk("%s: region already allocated at 0x%04x.\n", dev->name,
(u_short)iobase);
}
}
}
-
+
return;
}
@@ -1813,8 +1966,16 @@
struct device *adev = NULL;
int fixed = 0, new_dev = 0;
+ if (!dev) return dev;
num_eth = de4x5_dev_index(dev->name);
- if (loading_module) return dev;
+
+ if (loading_module) {
+ if (dev->priv) {
+ dev = insert_device(dev, iobase, de4x5_probe);
+ }
+ num_eth++;
+ return dev;
+ }
while (1) {
if (((dev->base_addr == DE4X5_NDA) || (dev->base_addr==0)) && !adev) {
@@ -1838,13 +1999,13 @@
new_dev = 0;
}
- if (((dev->next == NULL) &&
+ if (((dev->next == NULL) &&
((dev->base_addr != DE4X5_NDA) && (dev->base_addr != 0)) && !fixed) ||
new_dev) {
num_eth++; /* New device */
dev = insert_device(dev, iobase, de4x5_probe);
}
-
+
return dev;
}
@@ -1862,20 +2023,22 @@
printk("eth%d: Device not initialised, insufficient memory\n",num_eth);
return NULL;
} else {
- new->next = dev->next;
- dev->next = new;
- dev = dev->next; /* point to the new device */
- dev->name = (char *)(dev + 1);
- if (num_eth > 9999) {
- sprintf(dev->name,"eth????");/* New device name */
- } else {
- sprintf(dev->name,"eth%d", num_eth);/* New device name */
+ memset((char *)new, 0, sizeof(struct device)+8);
+ new->name = (char *)(new + 1);
+ new->base_addr = iobase; /* assign the io address */
+ new->init = init; /* initialisation routine */
+ if (!loading_module) {
+ new->next = dev->next;
+ dev->next = new;
+ if (num_eth > 9999) {
+ sprintf(new->name,"eth????");/* New device name */
+ } else {
+ sprintf(new->name,"eth%d", num_eth);/* New device name */
+ }
}
- dev->base_addr = iobase; /* assign the io address */
- dev->init = init; /* initialisation routine */
}
- return dev;
+ return new;
}
static int
@@ -1893,11 +2056,54 @@
return i;
}
+static void
+link_modules(struct device *dev, struct device *tmp)
+{
+ struct device *p=dev;
+
+ if (p) {
+ while (((struct de4x5_private *)(p->priv))->next_module) {
+ p = ((struct de4x5_private *)(p->priv))->next_module;
+ }
+
+ if (dev != tmp) {
+ ((struct de4x5_private *)(p->priv))->next_module = tmp;
+ } else {
+ ((struct de4x5_private *)(p->priv))->next_module = NULL;
+ }
+ }
+
+ return;
+}
+
+static struct device *
+unlink_modules(struct device *p)
+{
+ struct device *next = NULL;
+
+ if (p->priv) { /* Private areas allocated? */
+ struct de4x5_private *lp = (struct de4x5_private *)p->priv;
+
+ next = lp->next_module;
+ if (lp->cache.buf) { /* MAC buffers allocated? */
+ kfree(lp->cache.buf); /* Free the MAC buffers */
+ }
+ kfree(lp->cache.priv); /* Free the private area */
+ release_region(p->base_addr, (lp->bus == PCI ?
+ DE4X5_PCI_TOTAL_SIZE :
+ DE4X5_EISA_TOTAL_SIZE));
+ }
+ unregister_netdev(p);
+ kfree(p); /* Free the device structure */
+
+ return next;
+}
+
/*
** Auto configure the media here rather than setting the port at compile
** time. This routine is called by de4x5_init() and when a loss of media is
** detected (excessive collisions, loss of carrier, no carrier or link fail
-** [TP] or no recent receive activity) to check whether the user has been
+** [TP] or no recent receive activity) to check whether the user has been
** sneaky and changed the port on us.
*/
static int
@@ -1906,21 +2112,24 @@
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
u_long iobase = dev->base_addr;
int next_tick = DE4X5_AUTOSENSE_MS;;
-
+
lp->linkOK = 0;
lp->c_media = AUTO; /* Bogus last media */
disable_ast(dev);
inl(DE4X5_MFC); /* Zero the lost frames counter */
lp->media = INIT;
- if (lp->chipset == DC21040) {
+ if (lp->useSROM) {
+ next_tick = srom_autoconf(dev);
+ } else if (lp->chipset == DC21040) {
next_tick = dc21040_autoconf(dev);
} else if (lp->chipset == DC21041) {
next_tick = dc21041_autoconf(dev);
} else if (lp->chipset == DC21140) {
next_tick = dc21140m_autoconf(dev);
}
- enable_ast(dev, next_tick);
+ enable_ast(dev, next_tick);
+
return (lp->media);
}
@@ -1943,7 +2152,7 @@
u_long iobase = dev->base_addr;
int next_tick = DE4X5_AUTOSENSE_MS;
s32 imr;
-
+
switch (lp->media) {
case INIT:
DISABLE_IRQs;
@@ -1962,36 +2171,36 @@
lp->local_state = 0;
next_tick = dc21040_autoconf(dev);
break;
-
+
case TP:
- next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
+ next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
TP_SUSPECT, test_tp);
break;
-
+
case TP_SUSPECT:
next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
break;
-
+
case BNC:
case AUI:
case BNC_AUI:
- next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
+ next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
BNC_AUI_SUSPECT, ping_media);
break;
-
+
case BNC_AUI_SUSPECT:
next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
break;
-
+
case EXT_SIA:
- next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
+ next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
NC, EXT_SIA_SUSPECT, ping_media);
break;
-
+
case EXT_SIA_SUSPECT:
next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
break;
-
+
case NC:
/* default to TP for all */
reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
@@ -2003,13 +2212,13 @@
lp->tx_enable = NO;
break;
}
-
+
return next_tick;
}
static int
dc21040_state(struct device *dev, int csr13, int csr14, int csr15, int timeout,
- int next_state, int suspect_state,
+ int next_state, int suspect_state,
int (*fn)(struct device *, int))
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
@@ -2022,7 +2231,7 @@
lp->local_state++;
next_tick = 500;
break;
-
+
case 1:
if (!lp->tx_enable) {
linkBad = fn(dev, timeout);
@@ -2042,7 +2251,7 @@
}
break;
}
-
+
return next_tick;
}
@@ -2057,7 +2266,7 @@
switch (lp->local_state) {
case 1:
- if (lp->linkOK && !LOST_MEDIA) {
+ if (lp->linkOK) {
lp->media = prev_state;
} else {
lp->local_state++;
@@ -2096,7 +2305,7 @@
u_long iobase = dev->base_addr;
s32 sts, irqs, irq_mask, imr, omr;
int next_tick = DE4X5_AUTOSENSE_MS;
-
+
switch (lp->media) {
case INIT:
DISABLE_IRQs;
@@ -2117,11 +2326,11 @@
lp->local_state = 0;
next_tick = dc21041_autoconf(dev);
break;
-
+
case TP_NW:
if (lp->timeout < 0) {
omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
- outl(omr | OMR_FD, DE4X5_OMR);
+ outl(omr | OMR_FDX, DE4X5_OMR);
}
irqs = STS_LNF | STS_LNP;
irq_mask = IMR_LFM | IMR_LPM;
@@ -2137,7 +2346,7 @@
next_tick = dc21041_autoconf(dev);
}
break;
-
+
case ANS:
if (!lp->tx_enable) {
irqs = STS_LNP;
@@ -2159,16 +2368,16 @@
next_tick = 3000;
}
break;
-
+
case ANS_SUSPECT:
next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
break;
-
+
case TP:
if (!lp->tx_enable) {
if (lp->timeout < 0) {
omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
- outl(omr & ~OMR_FD, DE4X5_OMR);
+ outl(omr & ~OMR_FDX, DE4X5_OMR);
}
irqs = STS_LNF | STS_LNP;
irq_mask = IMR_LFM | IMR_LPM;
@@ -2193,16 +2402,16 @@
next_tick = 3000;
}
break;
-
+
case TP_SUSPECT:
next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
break;
-
+
case AUI:
if (!lp->tx_enable) {
if (lp->timeout < 0) {
omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
- outl(omr & ~OMR_FD, DE4X5_OMR);
+ outl(omr & ~OMR_FDX, DE4X5_OMR);
}
irqs = 0;
irq_mask = 0;
@@ -2223,17 +2432,17 @@
next_tick = 3000;
}
break;
-
+
case AUI_SUSPECT:
next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
break;
-
+
case BNC:
switch (lp->local_state) {
case 0:
if (lp->timeout < 0) {
omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
- outl(omr & ~OMR_FD, DE4X5_OMR);
+ outl(omr & ~OMR_FDX, DE4X5_OMR);
}
irqs = 0;
irq_mask = 0;
@@ -2245,7 +2454,7 @@
next_tick = dc21041_autoconf(dev);
}
break;
-
+
case 1:
if (!lp->tx_enable) {
if ((sts = ping_media(dev, 3000)) < 0) {
@@ -2265,14 +2474,14 @@
break;
}
break;
-
+
case BNC_SUSPECT:
next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
break;
-
+
case NC:
omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
- outl(omr | OMR_FD, DE4X5_OMR);
+ outl(omr | OMR_FDX, DE4X5_OMR);
reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
if (lp->media != lp->c_media) {
de4x5_dbg_media(dev);
@@ -2282,7 +2491,7 @@
lp->tx_enable = NO;
break;
}
-
+
return next_tick;
}
@@ -2300,38 +2509,43 @@
u_long imr, omr;
switch(lp->media) {
- case INIT:
+ case INIT:
DISABLE_IRQs;
lp->tx_enable = FALSE;
- lp->timeout = -1;
+ lp->linkOK = 0;
+/* lp->timeout = -1;*/
if ((next_tick = de4x5_reset_phy(dev)) < 0) {
next_tick &= ~TIMER_CB;
} else {
de4x5_save_skbs(dev); /* Save non transmitted skb's */
- lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
- SET_10Mb;
- if (lp->autosense == _100Mb) {
- lp->media = _100Mb;
- } else if (lp->autosense == _10Mb) {
- lp->media = _10Mb;
- } else if ((lp->autosense == AUTO) &&
- ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
- ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
- ana &= (de4x5_full_duplex ? ~0 : ~MII_ANA_FDAM);
- mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
- lp->media = ANS;
- } else if (lp->autosense == AUTO) {
- lp->media = SPD_DET;
- } else if (is_spd_100(dev) && is_100_up(dev)) {
- lp->media = _100Mb;
+ if (lp->useSROM) {
+ srom_map_media(dev);
} else {
- lp->media = NC;
+ lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
+ SET_10Mb;
+ if (lp->autosense == _100Mb) {
+ lp->media = _100Mb;
+ } else if (lp->autosense == _10Mb) {
+ lp->media = _10Mb;
+ } else if ((lp->autosense == AUTO) &&
+ ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
+ ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
+ ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
+ mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
+ lp->media = ANS;
+ } else if (lp->autosense == AUTO) {
+ lp->media = SPD_DET;
+ } else if (is_spd_100(dev) && is_100_up(dev)) {
+ lp->media = _100Mb;
+ } else {
+ lp->media = NC;
+ }
}
lp->local_state = 0;
next_tick = dc21140m_autoconf(dev);
}
break;
-
+
case ANS:
switch (lp->local_state) {
case 0:
@@ -2351,7 +2565,7 @@
next_tick = dc21140m_autoconf(dev);
}
break;
-
+
case 1:
if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
next_tick = sr & ~TIMER_CB;
@@ -2362,13 +2576,13 @@
lp->tmp = MII_SR_ASSC;
anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
- if (!(anlpa & MII_ANLPA_RF) &&
+ if (!(anlpa & MII_ANLPA_RF) &&
(cap = anlpa & MII_ANLPA_TAF & ana)) {
if (cap & MII_ANA_100M) {
- de4x5_full_duplex = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
+ lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
lp->media = _100Mb;
} else if (cap & MII_ANA_10M) {
- de4x5_full_duplex = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
+ lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
lp->media = _10Mb;
}
@@ -2379,7 +2593,7 @@
break;
}
break;
-
+
case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
if (lp->timeout < 0) {
lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
@@ -2399,9 +2613,9 @@
next_tick = dc21140m_autoconf(dev);
}
break;
-
+
case _100Mb: /* Set 100Mb/s */
- next_tick = 3000;
+ next_tick = 3000;
if (!lp->tx_enable) {
SET_100Mb;
de4x5_init_connection(dev);
@@ -2409,14 +2623,15 @@
if (!lp->linkOK && (lp->autosense == AUTO)) {
if (!(is_spd_100(dev) && is_100_up(dev))) {
lp->media = INIT;
+ lp->tcount++;
next_tick = DE4X5_AUTOSENSE_MS;
}
}
}
break;
-
+
case _10Mb: /* Set 10Mb/s */
- next_tick = 3000;
+ next_tick = 3000;
if (!lp->tx_enable) {
SET_10Mb;
de4x5_init_connection(dev);
@@ -2424,12 +2639,13 @@
if (!lp->linkOK && (lp->autosense == AUTO)) {
if (!(!is_spd_100(dev) && is_10_up(dev))) {
lp->media = INIT;
+ lp->tcount++;
next_tick = DE4X5_AUTOSENSE_MS;
}
}
}
break;
-
+
case NC:
if (lp->media != lp->c_media) {
de4x5_dbg_media(dev);
@@ -2439,10 +2655,76 @@
lp->tx_enable = FALSE;
break;
}
-
+
return next_tick;
}
+static int
+srom_autoconf(struct device *dev)
+{
+ struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
+
+ return lp->infoleaf_fn(dev);
+}
+
+/*
+** This mapping keeps the original media codes and FDX flag unchanged.
+** While it isn't strictly necessary, it helps me for the moment...
+*/
+static void
+srom_map_media(struct device *dev)
+{
+ struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
+
+ lp->fdx = 0;
+ switch(lp->infoblock_media) {
+ case SROM_10BASETF:
+ lp->fdx = TRUE;
+ case SROM_10BASET:
+ if (lp->chipset == DC21140) {
+ lp->media = _10Mb;
+ } else {
+ lp->media = TP;
+ }
+ break;
+
+ case SROM_10BASE2:
+ lp->media = BNC;
+ break;
+
+ case SROM_10BASE5:
+ lp->media = AUI;
+ break;
+
+ case SROM_100BASETF:
+ lp->fdx = TRUE;
+ case SROM_100BASET:
+ lp->media = _100Mb;
+ break;
+
+ case SROM_100BASET4:
+ lp->media = _100Mb;
+ break;
+
+ case SROM_100BASEFF:
+ lp->fdx = TRUE;
+ case SROM_100BASEF:
+ lp->media = _100Mb;
+ break;
+
+ case ANS:
+ lp->media = ANS;
+ break;
+
+ default:
+ printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
+ lp->infoblock_media);
+ break;
+ }
+
+ return;
+}
+
static void
de4x5_init_connection(struct device *dev)
{
@@ -2457,7 +2739,6 @@
cli();
de4x5_rx(dev);
de4x5_setup_intr(dev);
- lp->lostMedia = 0;
lp->tx_enable = YES;
dev->tbusy = 0;
sti();
@@ -2467,6 +2748,9 @@
return;
}
+/*
+** General PHY reset function.
+*/
static int
de4x5_reset_phy(struct device *dev)
{
@@ -2474,15 +2758,26 @@
u_long iobase = dev->base_addr;
int next_tick = 0;
- if (lp->phy[lp->active].id) {
+ if ((lp->useSROM) || (lp->phy[lp->active].id)) {
if (lp->timeout < 0) {
- outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */
- udelay(1000); /* Assert for 1ms */
- outl(0x00, DE4X5_GEP);
- udelay(2000); /* Wait for 2ms */
- mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
+ if (lp->useSROM) {
+ if (lp->phy[lp->active].rst) { /* MII device specific reset */
+ srom_exec(dev, lp->phy[lp->active].rst);
+ } else if (lp->rst) { /* Type 5 infoblock reset */
+ srom_exec(dev, lp->rst);
+ }
+ } else {
+ PHY_HARD_RESET;
+ }
+ if (lp->useMII) {
+ mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
+ }
+ }
+ if (lp->useMII) {
+ next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
}
- next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
+ } else if (lp->chipset == DC21140) {
+ PHY_HARD_RESET;
}
return next_tick;
@@ -2494,7 +2789,7 @@
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
u_long iobase = dev->base_addr;
s32 sts, csr12;
-
+
if (lp->timeout < 0) {
lp->timeout = msec/100;
reset_init_sia(dev, csr13, csr14, csr15);
@@ -2505,22 +2800,22 @@
/* clear all pending interrupts */
sts = inl(DE4X5_STS);
outl(sts, DE4X5_STS);
-
+
/* clear csr12 NRA and SRA bits */
if (lp->chipset == DC21041) {
csr12 = inl(DE4X5_SISR);
outl(csr12, DE4X5_SISR);
}
}
-
+
sts = inl(DE4X5_STS) & ~TIMER_CB;
-
+
if (!(sts & irqs) && --lp->timeout) {
sts = 100 | TIMER_CB;
} else {
lp->timeout = -1;
}
-
+
return sts;
}
@@ -2530,11 +2825,11 @@
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
u_long iobase = dev->base_addr;
int sisr;
-
+
if (lp->timeout < 0) {
lp->timeout = msec/100;
}
-
+
sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
if (sisr && --lp->timeout) {
@@ -2542,7 +2837,7 @@
} else {
lp->timeout = -1;
}
-
+
return sisr;
}
@@ -2552,12 +2847,12 @@
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
int iobase = dev->base_addr;
int gep = 0;
-
+
if (lp->timeout < 0) {
lp->timeout = msec/100;
}
-
- if (lp->phy[lp->active].id) {
+
+ if (lp->phy[lp->active].id || lp->useSROM) {
gep = ((is_100_up(dev) && is_spd_100(dev)) ? GEP_SLNK : 0);
} else {
gep = (~inl(DE4X5_GEP) & (GEP_SLNK | GEP_LNP));
@@ -2567,7 +2862,7 @@
} else {
lp->timeout = -1;
}
-
+
return gep;
}
@@ -2580,21 +2875,21 @@
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
int test, iobase = dev->base_addr;
-
+
if (lp->timeout < 0) {
lp->timeout = msec/100;
}
-
+
if (pol) pol = ~0;
reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
test = (reg ^ pol) & mask;
-
+
if (test && --lp->timeout) {
reg = 100 | TIMER_CB;
} else {
lp->timeout = -1;
}
-
+
return reg;
}
@@ -2604,15 +2899,19 @@
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
u_long iobase = dev->base_addr;
int spd;
-
- if (lp->phy[lp->active].id) {
+
+ if (lp->useSROM && !lp->useMII) {
+ spd = (lp->asBitValid &
+ (lp->asPolarity ^ (inl(DE4X5_GEP) & lp->asBit))) |
+ (lp->linkOK & ~lp->asBitValid);
+ } else if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
spd = ~(spd ^ lp->phy[lp->active].spd.value);
spd &= lp->phy[lp->active].spd.mask;
} else {
spd = ((~inl(DE4X5_GEP)) & GEP_SLNK);
}
-
+
return spd;
}
@@ -2621,8 +2920,12 @@
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
u_long iobase = dev->base_addr;
-
- if (lp->phy[lp->active].id) {
+
+ if (lp->useSROM && !lp->useMII) {
+ return ((lp->asBitValid &
+ (lp->asPolarity ^ (inl(DE4X5_GEP) & lp->asBit))) |
+ (lp->linkOK & ~lp->asBitValid));
+ } else if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
/* Double read for sticky bits & temporary drops */
mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
@@ -2636,8 +2939,12 @@
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
u_long iobase = dev->base_addr;
-
- if (lp->phy[lp->active].id) {
+
+ if (lp->useSROM && !lp->useMII) {
+ return ((lp->asBitValid &
+ (lp->asPolarity ^ (inl(DE4X5_GEP) & lp->asBit))) |
+ (lp->linkOK & ~lp->asBitValid));
+ } else if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
/* Double read for sticky bits & temporary drops */
mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
@@ -2651,8 +2958,8 @@
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
u_long iobase = dev->base_addr;
-
- if (lp->phy[lp->active].id) {
+
+ if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
} else {
return 0;
@@ -2669,24 +2976,24 @@
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
u_long iobase = dev->base_addr;
int sisr;
-
+
if (lp->timeout < 0) {
lp->timeout = msec/100;
-
+
lp->tmp = lp->tx_new; /* Remember the ring position */
load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), NULL);
lp->tx_new = (++lp->tx_new) % lp->txRingSize;
outl(POLL_DEMAND, DE4X5_TPD);
}
-
+
sisr = inl(DE4X5_SISR);
- if ((!(sisr & SISR_NCR)) &&
- ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
+ if ((!(sisr & SISR_NCR)) &&
+ ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
(--lp->timeout)) {
sisr = 100 | TIMER_CB;
} else {
- if ((!(sisr & SISR_NCR)) &&
+ if ((!(sisr & SISR_NCR)) &&
!(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
lp->timeout) {
sisr = 0;
@@ -2695,7 +3002,7 @@
}
lp->timeout = -1;
}
-
+
return sisr;
}
@@ -2742,15 +3049,15 @@
skb_reserve(p, 2); /* Align */
if (index < lp->rx_old) { /* Wrapped buffer */
short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
- memcpy(skb_put(p,tlen),
+ memcpy(skb_put(p,tlen),
bus_to_virt(le32_to_cpu(lp->rx_ring[lp->rx_old].buf)),tlen);
- memcpy(skb_put(p,len-tlen),
+ memcpy(skb_put(p,len-tlen),
bus_to_virt(le32_to_cpu(lp->rx_ring[0].buf)), len-tlen);
} else { /* Linear buffer */
- memcpy(skb_put(p,len),
+ memcpy(skb_put(p,len),
bus_to_virt(le32_to_cpu(lp->rx_ring[lp->rx_old].buf)),len);
}
-
+
return p;
#endif
}
@@ -2837,7 +3144,7 @@
lp->cache.save_cnt--;
START_DE4X5;
}
-
+
return;
}
@@ -2846,7 +3153,6 @@
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
u_long iobase = dev->base_addr;
- s32 gep;
switch(flag) {
case DE4X5_SAVE_STATE:
@@ -2865,14 +3171,10 @@
outl(lp->cache.csr6, DE4X5_OMR);
outl(lp->cache.csr7, DE4X5_IMR);
if (lp->chipset == DC21140) {
- outl(GEP_INIT, DE4X5_GEP);
- gep = (lp->media == _100Mb ? GEP_MODE : 0);
- if (!lp->phy[lp->active].id && !de4x5_full_duplex) {
- gep |= GEP_FDXD;
- }
- outl(gep, DE4X5_GEP);
+ outl(lp->cache.gepc, DE4X5_GEP);
+ outl(lp->cache.gep, DE4X5_GEP);
} else {
- reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
+ reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
lp->cache.csr15);
}
break;
@@ -2934,25 +3236,25 @@
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
u_long iobase = dev->base_addr;
s32 sts, ans;
-
+
if (lp->timeout < 0) {
lp->timeout = msec/100;
outl(irq_mask, DE4X5_IMR);
-
+
/* clear all pending interrupts */
sts = inl(DE4X5_STS);
outl(sts, DE4X5_STS);
}
-
+
ans = inl(DE4X5_SISR) & SISR_ANS;
sts = inl(DE4X5_STS) & ~TIMER_CB;
-
+
if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
sts = 100 | TIMER_CB;
} else {
lp->timeout = -1;
}
-
+
return sts;
}
@@ -2962,7 +3264,7 @@
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
u_long iobase = dev->base_addr;
s32 imr, sts;
-
+
if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
imr = 0;
UNMASK_IRQs;
@@ -2970,7 +3272,7 @@
outl(sts, DE4X5_STS);
ENABLE_IRQs;
}
-
+
return;
}
@@ -2982,7 +3284,7 @@
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
u_long iobase = dev->base_addr;
-
+
RESET_SIA;
outl(sigr, DE4X5_SIGR);
outl(strr, DE4X5_STRR);
@@ -2992,24 +3294,24 @@
}
/*
-** Create a loopback ethernet packet with an invalid CRC
+** Create a loopback ethernet packet
*/
static void
create_packet(struct device *dev, char *frame, int len)
{
int i;
char *buf = frame;
-
+
for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
*buf++ = dev->dev_addr[i];
}
for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
*buf++ = dev->dev_addr[i];
}
-
+
*buf++ = 0; /* Packet length (2 bytes) */
*buf++ = 1;
-
+
return;
}
@@ -3020,7 +3322,7 @@
de4x5_us_delay(u32 usec)
{
udelay(usec);
-
+
return;
}
@@ -3031,11 +3333,11 @@
de4x5_ms_delay(u32 msec)
{
u_int i;
-
+
for (i=0; i<msec; i++) {
de4x5_us_delay(1000);
}
-
+
return;
}
@@ -3053,17 +3355,17 @@
char Id[4];
} Eisa;
int i, status = 0, siglen = sizeof(signatures)/sizeof(c_char *);
-
+
*name = '\0';
Eisa.ID = inl(eisa_id);
-
+
ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
ManCode[5]='\0';
-
+
for (i=0;i<siglen;i++) {
if (strstr(ManCode, signatures[i]) != NULL) {
strcpy(name,ManCode);
@@ -3071,7 +3373,7 @@
break;
}
}
-
+
return status; /* return the device name string */
}
@@ -3083,16 +3385,13 @@
{
c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
-
+
if (lp->chipset == DC21040) {
strcpy(name, "DE434/5");
- } else {
+ return status;
+ } else { /* Search for a DEC name in the SROM */
int i = *((char *)&lp->srom + 19) * 3;
- if (lp->chipset == DC21041) {
- strncpy(name, (char *)&lp->srom + 26 + i, 8);
- } else if (lp->chipset == DC21140) {
- strncpy(name, (char *)&lp->srom + 26 + i, 8);
- }
+ strncpy(name, (char *)&lp->srom + 26 + i, 8);
}
name[8] = '\0';
for (i=0; i<siglen; i++) {
@@ -3104,11 +3403,16 @@
} else { /* Use chip name to avoid confusion */
strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
((lp->chipset == DC21041) ? "DC21041" :
- ((lp->chipset == DC21140) ? "DC21140" : "UNKNOWN"
- )))));
+ ((lp->chipset == DC21140) ? "DC21140" :
+ ((lp->chipset == DC21142) ? "DC21142" :
+ ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
+ )))))));
+ }
+ if (lp->chipset != DC21041) {
+ useSROM = TRUE; /* card is not recognisably DEC */
}
}
-
+
return status;
}
@@ -3121,7 +3425,7 @@
{
int i;
struct bus_type *lp = &bus;
-
+
if (lp->chipset == DC21040) {
outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
} else { /* Read new srom */
@@ -3131,10 +3435,16 @@
}
de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
}
-
+
return;
}
+/*
+** For the bad status case and no SROM, then add one to the previous
+** address. However, need to add one backwards in case we have 0xff
+** as one or more of the bytes. Only the last 3 bytes should be checked
+** as the first three are invariant - assigned to an organisation.
+*/
static int
get_hw_addr(struct device *dev)
{
@@ -3147,7 +3457,7 @@
for (i=0,k=0,j=0;j<3;j++) {
k <<= 1;
if (k > 0xffff) k-=0xffff;
-
+
if (lp->bus == PCI) {
if (lp->chipset == DC21040) {
while ((tmp = inl(DE4X5_APROM)) < 0);
@@ -3169,11 +3479,11 @@
k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
dev->dev_addr[i++] = (u_char) tmp;
}
-
+
if (k > 0xffff) k-=0xffff;
}
if (k == 0xffff) k=0;
-
+
if (lp->bus == PCI) {
if (lp->chipset == DC21040) {
while ((tmp = inl(DE4X5_APROM)) < 0);
@@ -3188,6 +3498,12 @@
if ((k != chksum) && (dec_only)) status = -1;
}
+ /* If possible, try to fix a broken card - SMC only so far */
+ srom_repair(dev, broken);
+
+ /* Test for a bad enet address */
+ status = test_bad_enet(dev, status);
+
return status;
}
@@ -3227,6 +3543,55 @@
return ret;
}
+static void
+srom_repair(struct device *dev, int card)
+{
+ struct bus_type *lp = &bus;
+
+ switch(card) {
+ case SMC:
+ memset((char *)&bus.srom, 0, sizeof(struct de4x5_srom));
+ memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
+ memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
+ useSROM = TRUE;
+ break;
+ }
+
+ return;
+}
+
+static int
+test_bad_enet(struct device *dev, int status)
+{
+ struct bus_type *lp = &bus;
+ int i, tmp;
+
+ for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
+ if ((tmp == 0) || (tmp == 0x5fa)) {
+ if ((lp->chipset == last.chipset) &&
+ (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
+ for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
+ for (i=ETH_ALEN-1; i>2; --i) {
+ dev->dev_addr[i] += 1;
+ if (dev->dev_addr[i] != 0) break;
+ }
+ for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
+ if (((*((int *)dev->dev_addr) & 0x00ffffff) == 0x95c000) &&
+ (lp->chipset == DC21040)) {
+ dev->irq = last.irq;
+ }
+ status = 0;
+ }
+ } else if (!status) {
+ last.chipset = lp->chipset;
+ last.bus = lp->bus_num;
+ last.irq = dev->irq;
+ for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
+ }
+
+ return status;
+}
+
/*
** SROM Read
*/
@@ -3234,11 +3599,11 @@
srom_rd(u_long addr, u_char offset)
{
sendto_srom(SROM_RD | SROM_SR, addr);
-
+
srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
-
+
return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
}
@@ -3248,7 +3613,7 @@
sendto_srom(command, addr);
sendto_srom(command | DT_CLK, addr);
sendto_srom(command, addr);
-
+
return;
}
@@ -3258,7 +3623,7 @@
srom_latch(command, addr);
srom_latch(command, addr);
srom_latch((command & 0x0000ff00) | DT_CS, addr);
-
+
return;
}
@@ -3267,18 +3632,18 @@
{
int i;
char a;
-
+
a = (char)(offset << 2);
for (i=0; i<6; i++, a <<= 1) {
srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
}
de4x5_us_delay(1);
-
+
i = (getfrom_srom(addr) >> 3) & 0x01;
if (i != 0) {
printk("Bad SROM address phase.....\n");
}
-
+
return;
}
@@ -3288,17 +3653,17 @@
int i;
short word = 0;
s32 tmp;
-
+
for (i=0; i<16; i++) {
sendto_srom(command | DT_CLK, addr);
tmp = getfrom_srom(addr);
sendto_srom(command, addr);
-
+
word = (word << 1) | ((tmp >> 3) & 0x01);
}
-
+
sendto_srom(command & 0x0000ff00, addr);
-
+
return word;
}
@@ -3307,13 +3672,13 @@
srom_busy(u_int command, u_long addr)
{
sendto_srom((command & 0x0000ff00) | DT_CS, addr);
-
+
while (!((getfrom_srom(addr) >> 3) & 0x01)) {
de4x5_ms_delay(1);
}
-
+
sendto_srom(command & 0x0000ff00, addr);
-
+
return;
}
*/
@@ -3323,7 +3688,7 @@
{
outl(command, addr);
udelay(1);
-
+
return;
}
@@ -3331,13 +3696,406 @@
getfrom_srom(u_long addr)
{
s32 tmp;
-
+
tmp = inl(addr);
udelay(1);
-
+
return tmp;
}
+static int
+srom_infoleaf_info(struct device *dev)
+{
+ struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
+ int i, count;
+ u_char *p;
+
+ /* Find the infoleaf decoder function that matches this chipset */
+ for (i=0; i<INFOLEAF_SIZE; i++) {
+ if (lp->chipset == infoleaf_array[i].chipset) break;
+ }
+ if (i == INFOLEAF_SIZE) {
+ lp->useSROM = FALSE;
+ printk("%s: Cannot find correct chipset for SROM decoding!\n",
+ dev->name);
+ return -ENXIO;
+ }
+
+ lp->infoleaf_fn = infoleaf_array[i].fn;
+
+ /* Find the information offset that this function should use */
+ count = *((u_char *)&lp->srom + 19);
+ p = (u_char *)&lp->srom + 26;
+
+ if (count > 1) {
+ for (i=count; i; --i, p+=3) {
+ if (lp->device == *p) break;
+ }
+ if (i == 0) {
+ lp->useSROM = FALSE;
+ printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
+ dev->name, lp->device);
+ return -ENXIO;
+ }
+ }
+
+ lp->infoleaf_offset = (u_short)*((u_short *)(p+1));
+
+ return 0;
+}
+
+/*
+** This routine loads any type 1 or 3 MII info into the mii device
+** struct and executes any type 5 code to reset PHY devices for this
+** controller.
+** The info for the MII devices will be valid since the index used
+** will follow the discovery process from MII address 1-31 then 0.
+*/
+static void
+srom_init(struct device *dev)
+{
+ struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
+ u_long iobase = dev->base_addr;
+ u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
+ u_char count;
+
+ if (lp->chipset == DC21140) {
+ p+=2;
+ lp->cache.gepc = (*p++ | GEP_CTRL);
+ outl(lp->cache.gepc, DE4X5_GEP);
+ } else if (lp->chipset == DC21142) {
+ p+=2;
+ } else if (lp->chipset == DC21143) {
+ p+=2;
+ }
+
+ /* Block count */
+ count = *p++;
+
+ /* Jump the infoblocks to find types */
+ for (;count; --count) {
+ if (*p < 128) {
+ p += COMPACT_LEN;
+ } else if (*(p+1) == 5) {
+ type5_infoblock(dev, 1, p);
+ p += ((*p & BLOCK_LEN) + 1);
+ } else if (*(p+1) == 3) {
+ type3_infoblock(dev, 1, p);
+ p += ((*p & BLOCK_LEN) + 1);
+ } else if (*(p+1) == 1) {
+ type1_infoblock(dev, 1, p);
+ p += ((*p & BLOCK_LEN) + 1);
+ } else {
+ p += ((*p & BLOCK_LEN) + 1);
+ }
+ }
+
+ return;
+}
+
+static void
+srom_exec(struct device *dev, u_char *p)
+{
+ struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
+ u_long iobase = dev->base_addr;
+ u_char count = *p++;
+
+ while (count--) {
+ if (lp->chipset == DC21140) {
+ outl(*p++, DE4X5_GEP);
+ }
+ udelay(2000); /* 2ms per action */
+ }
+
+ return;
+}
+
+/*
+** Basically this function is a NOP since it will never be called,
+** unless I implement the DC21041 SROM functions. There's no need
+** since the existing code will be satisfactory for all boards.
+*/
+static int
+dc21041_infoleaf(struct device *dev)
+{
+ return DE4X5_AUTOSENSE_MS;
+}
+
+static int
+dc21140_infoleaf(struct device *dev)
+{
+ struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
+ u_char count = 0;
+ u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
+ int next_tick = DE4X5_AUTOSENSE_MS;
+
+ /* Read the connection type */
+ p+=2;
+
+ /* GEP control */
+ lp->cache.gepc = (*p++ | GEP_CTRL);
+
+ /* Block count */
+ count = *p++;
+
+ /* Recursively figure out the info blocks */
+ if (*p < 128) {
+ next_tick = dc_infoblock[COMPACT](dev, count, p);
+ } else {
+ next_tick = dc_infoblock[*(p+1)](dev, count, p);
+ }
+
+ if (lp->tcount == count) {
+ lp->media = NC;
+ if (lp->media != lp->c_media) {
+ de4x5_dbg_media(dev);
+ lp->c_media = lp->media;
+ }
+ lp->media = INIT;
+ lp->tcount = 0;
+ lp->tx_enable = FALSE;
+ }
+
+ return next_tick & ~TIMER_CB;
+}
+
+static int
+dc21142_infoleaf(struct device *dev)
+{
+printk("dc21142_infoleaf()\n");
+ return DE4X5_AUTOSENSE_MS;
+}
+
+static int
+dc21143_infoleaf(struct device *dev)
+{
+printk("dc21143_infoleaf()\n");
+ return DE4X5_AUTOSENSE_MS;
+}
+
+/*
+** The compact infoblock is only designed for DC21140[A] chips, so
+** we'll reuse the dc21140m_autoconf function. Non MII media only.
+*/
+static int
+compact_infoblock(struct device *dev, u_char count, u_char *p)
+{
+ struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
+ u_long iobase = dev->base_addr;
+ u_char flags, csr6;
+
+ /* Recursively figure out the info blocks */
+ if (--count > lp->tcount) {
+ if (*(p+COMPACT_LEN) < 128) {
+ return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
+ } else {
+ return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
+ }
+ }
+
+ if (lp->media == INIT) {
+ outl(lp->cache.gepc, DE4X5_GEP);
+ lp->infoblock_media = (*p++) & COMPACT_MC;
+ lp->cache.gep = *p++;
+ csr6 = *p++;
+ flags = *p++;
+
+ lp->asBitValid = (flags & 0x80) ? 0 : -1;
+ lp->defMedium = (flags & 0x40) ? -1 : 0;
+ lp->asBit = 1 << ((csr6 >> 1) & 0x07);
+ lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
+ lp->infoblock_csr6 = (csr6 & 0x71) << 18;
+ lp->useMII = FALSE;
+
+ de4x5_switch_mac_port(dev);
+ }
+
+ return dc21140m_autoconf(dev);
+}
+
+/*
+** This block describes non MII media for the DC21140[A] only.
+ */
+static int
+type0_infoblock(struct device *dev, u_char count, u_char *p)
+{
+ struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
+ u_long iobase = dev->base_addr;
+ u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
+
+ /* Recursively figure out the info blocks */
+ if (--count > lp->tcount) {
+ if (*(p+len) < 128) {
+ return dc_infoblock[COMPACT](dev, count, p+len);
+ } else {
+ return dc_infoblock[*(p+len+1)](dev, count, p+len);
+ }
+ }
+
+ if (lp->media == INIT) {
+ outl(lp->cache.gepc, DE4X5_GEP);
+ p+=2;
+ lp->infoblock_media = (*p++) & BLOCK0_MC;
+ lp->cache.gep = *p++;
+ csr6 = *p++;
+ flags = *p++;
+
+ lp->asBitValid = (flags & 0x80) ? 0 : -1;
+ lp->defMedium = (flags & 0x40) ? -1 : 0;
+ lp->asBit = 1 << ((csr6 >> 1) & 0x07);
+ lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
+ lp->infoblock_csr6 = (csr6 & 0x71) << 18;
+ lp->useMII = FALSE;
+
+ de4x5_switch_mac_port(dev);
+ }
+
+ return dc21140m_autoconf(dev);
+}
+
+/* These functions are under construction! */
+
+static int
+type1_infoblock(struct device *dev, u_char count, u_char *p)
+{
+ struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
+ u_long iobase = dev->base_addr;
+ u_char len = (*p & BLOCK_LEN)+1;
+ int ana;
+
+ /* Recursively figure out the info blocks */
+ if (--count > lp->tcount) {
+ if (*(p+len) < 128) {
+ return dc_infoblock[COMPACT](dev, count, p+len);
+ } else {
+ return dc_infoblock[*(p+len+1)](dev, count, p+len);
+ }
+ }
+
+ if (lp->state == INITIALISED) {
+ lp->ibn = 1; p += 2;
+ lp->active = *p++;
+ lp->phy[lp->active].gep = (*p ? p : 0); p += (*p + 1);
+ lp->phy[lp->active].rst = (*p ? p : 0); p += (*p + 1);
+ lp->phy[lp->active].mc = *(u_short *)p; p += 2;
+ lp->phy[lp->active].ana = *(u_short *)p; p += 2;
+ lp->phy[lp->active].fdx = *(u_short *)p; p += 2;
+ lp->phy[lp->active].ttm = *(u_short *)p;
+ return 0;
+ } else if (lp->media == INIT) {
+ if (lp->phy[lp->active].gep) {
+ srom_exec(dev, lp->phy[lp->active].gep);
+ }
+ ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
+ mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
+ lp->infoblock_csr6 = OMR_PS | OMR_HBD;
+ lp->useMII = TRUE;
+ lp->infoblock_media = ANS;
+ de4x5_switch_mac_port(dev);
+ }
+
+ return dc21140m_autoconf(dev);
+}
+
+static int
+type2_infoblock(struct device *dev, u_char count, u_char *p)
+{
+ return DE4X5_AUTOSENSE_MS;
+}
+
+static int
+type3_infoblock(struct device *dev, u_char count, u_char *p)
+{
+ struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
+ u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
+
+ /* Recursively figure out the info blocks */
+ if (--count > lp->tcount) {
+ if (*(p+len) < 128) {
+ return dc_infoblock[COMPACT](dev, count, p+len);
+ } else {
+ return dc_infoblock[*(p+len+1)](dev, count, p+len);
+ }
+ }
+
+ if (lp->state == INITIALISED) {
+ lp->ibn = 3; p += 2;
+ lp->active = *p++;
+ lp->phy[lp->active].gep = (*p ? p : 0); p += (*p + 1);
+ lp->phy[lp->active].rst = (*p ? p : 0); p += (*p + 1);
+ lp->phy[lp->active].mc = *(u_short *)p; p += 2;
+ lp->phy[lp->active].ana = *(u_short *)p; p += 2;
+ lp->phy[lp->active].fdx = *(u_short *)p; p += 2;
+ lp->phy[lp->active].ttm = *(u_short *)p;
+ return 0;
+ } else if (lp->media == INIT) {
+ p+=2;
+ lp->infoblock_media = (*p++) & BLOCK0_MC;
+ lp->cache.gep = *p++;
+ csr6 = *p++;
+ flags = *p++;
+
+ lp->asBitValid = (flags & 0x80) ? 0 : -1;
+ lp->defMedium = (flags & 0x40) ? -1 : 0;
+ lp->asBit = 1 << ((csr6 >> 1) & 0x07);
+ lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
+ lp->infoblock_csr6 = (csr6 & 0x71) << 18;
+ lp->useMII = TRUE;
+
+ de4x5_switch_mac_port(dev);
+ }
+
+ return dc21140m_autoconf(dev);
+}
+
+static int
+type4_infoblock(struct device *dev, u_char count, u_char *p)
+{
+ return DE4X5_AUTOSENSE_MS;
+}
+
+/*
+** This block type provides information for resetting external devices
+** (chips) through the General Purpose Register.
+*/
+static int
+type5_infoblock(struct device *dev, u_char count, u_char *p)
+{
+ struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
+ u_long iobase = dev->base_addr;
+ u_char i, j, len = (*p & BLOCK_LEN)+1;
+
+ /* Recursively figure out the info blocks */
+ if (--count > lp->tcount) {
+ if (*(p+len) < 128) {
+ return dc_infoblock[COMPACT](dev, count, p+len);
+ } else {
+ return dc_infoblock[*(p+len+1)](dev, count, p+len);
+ }
+ }
+
+ /* Must be initializing to run this code */
+ if ((lp->state == INITIALISED) || (lp->media == INIT)) {
+ p+=2;
+ lp->rst = p;
+ i = *p++;
+ for (j=0;i;--i) {
+ if (lp->chipset == DC21140) {
+ if (!j) {
+ outl(*p++ | GEP_CTRL, DE4X5_GEP);
+ j++;
+ }
+ outl(*p++, DE4X5_GEP);
+ } else if (lp->chipset == DC21142) {
+ } else if (lp->chipset == DC21143) {
+ }
+ }
+
+ }
+
+ return DE4X5_AUTOSENSE_MS;
+}
+
/*
** MII Read/Write
*/
@@ -3351,7 +4109,7 @@
mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
mii_address(phyreg, ioaddr); /* PHY Register to read */
mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
-
+
return mii_rdata(ioaddr); /* Read data */
}
@@ -3366,7 +4124,7 @@
mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
data = mii_swap(data, 16); /* Swap data bit ordering */
mii_wdata(data, 16, ioaddr); /* Write data */
-
+
return;
}
@@ -3375,12 +4133,12 @@
{
int i;
s32 tmp = 0;
-
+
for (i=0; i<16; i++) {
tmp <<= 1;
tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
}
-
+
return tmp;
}
@@ -3388,12 +4146,12 @@
mii_wdata(int data, int len, u_long ioaddr)
{
int i;
-
+
for (i=0; i<len; i++) {
sendto_mii(MII_MWR | MII_WR, data, ioaddr);
data >>= 1;
}
-
+
return;
}
@@ -3401,13 +4159,13 @@
mii_address(u_char addr, u_long ioaddr)
{
int i;
-
+
addr = mii_swap(addr, 5);
for (i=0; i<5; i++) {
sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
addr >>= 1;
}
-
+
return;
}
@@ -3415,12 +4173,12 @@
mii_ta(u_long rw, u_long ioaddr)
{
if (rw == MII_STWR) {
- sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
- sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
+ sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
+ sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
} else {
getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
}
-
+
return;
}
@@ -3428,13 +4186,13 @@
mii_swap(int data, int len)
{
int i, tmp = 0;
-
+
for (i=0; i<len; i++) {
tmp <<= 1;
tmp |= (data & 1);
data >>= 1;
}
-
+
return tmp;
}
@@ -3442,13 +4200,13 @@
sendto_mii(u32 command, int data, u_long ioaddr)
{
u32 j;
-
+
j = (data & 1) << 17;
outl(command | j, ioaddr);
udelay(1);
outl(command | MII_MDC | j, ioaddr);
udelay(1);
-
+
return;
}
@@ -3459,7 +4217,7 @@
udelay(1);
outl(command | MII_MDC, ioaddr);
udelay(1);
-
+
return ((inl(ioaddr) >> 19) & 1);
}
@@ -3511,24 +4269,26 @@
return r2; /* (I did it) My way */
}
+/*
+** The SROM spec forces us to search addresses [1-31 0]. Bummer.
+*/
static int
mii_get_phy(struct device *dev)
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
int iobase = dev->base_addr;
- int i, j, k, limit=sizeof(phy_info)/sizeof(struct phy_table);
+ int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
int id;
-
- /* Issue a hard PHY reset - Broadcom is screwed up otherwise */
- outl(GEP_HRST, DE4X5_GEP);
- udelay(1000); /* Assert for 1ms */
- outl(0x00, DE4X5_GEP);
- udelay(2000); /* Wait for 2ms */
+
+ lp->active = 0;
+ lp->useMII = TRUE;
/* Search the MII address space for possible PHY devices */
- lp->active = 0;
- for (lp->mii_cnt=0, i=1; i<DE4X5_MAX_MII; i++) {
- id = mii_get_oui(i, DE4X5_MII);
+ for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(++i)%DE4X5_MAX_MII) {
+ lp->phy[lp->active].addr = i;
+ if (i==0) n++; /* Count cycles */
+ while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
+ id = mii_get_oui(i, DE4X5_MII);
if ((id == 0) || (id == -1)) continue; /* Valid ID? */
for (j=0; j<limit; j++) { /* Search PHY table */
if (id != phy_info[j].id) continue; /* ID match? */
@@ -3538,21 +4298,23 @@
(char *)&phy_info[j], sizeof(struct phy_table));
lp->phy[k].addr = i;
lp->mii_cnt++;
+ lp->active++;
} else {
i = DE4X5_MAX_MII; /* Stop the search */
j = limit;
}
}
}
- if (lp->phy[lp->active].id) { /* Reset the PHY devices */
+ lp->active = 0;
+ if (lp->phy[0].id) { /* Reset the PHY devices */
for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
-
+
de4x5_dbg_mii(dev, k);
}
}
-
+
return lp->mii_cnt;
}
@@ -3562,12 +4324,12 @@
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
int i;
char *pa = lp->setup_frame;
-
+
/* Initialise the setup frame */
if (mode == ALL) {
memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
}
-
+
if (lp->setup_f == HASH_PERF) {
for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
*(pa + i) = dev->dev_addr[i]; /* Host address */
@@ -3584,7 +4346,7 @@
if (i & 0x01) pa += 4;
}
}
-
+
return pa; /* Points to the next entry */
}
@@ -3592,7 +4354,7 @@
enable_ast(struct device *dev, u32 time_out)
{
timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
-
+
return;
}
@@ -3600,60 +4362,33 @@
disable_ast(struct device *dev)
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
-
+
del_timer(&lp->timer);
-
+
return;
}
static long
-de4x5_switch_to_mii(struct device *dev)
+de4x5_switch_mac_port(struct device *dev)
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
int iobase = dev->base_addr;
- long omr;
+ s32 omr;
/* Assert the OMR_PS bit in CSR6 */
- omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR));
- omr |= (OMR_PS | OMR_HBD);
+ omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
+ OMR_FDX));
+ omr |= lp->infoblock_csr6;
+ if (omr & OMR_PS) omr |= OMR_HBD;
outl(omr, DE4X5_OMR);
-
+
/* Soft Reset */
RESET_DE4X5;
-
+
/* Restore the GEP */
if (lp->chipset == DC21140) {
- outl(GEP_INIT, DE4X5_GEP);
- outl(0, DE4X5_GEP);
- }
-
- /* Restore CSR6 */
- outl(omr, DE4X5_OMR);
-
- /* Reset CSR8 */
- inl(DE4X5_MFC);
-
- return omr;
-}
-
-static long
-de4x5_switch_to_srl(struct device *dev)
-{
- struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
- int iobase = dev->base_addr;
- long omr;
-
- /* Deassert the OMR_PS bit in CSR6 */
- omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR));
- outl(omr, DE4X5_OMR);
-
- /* Soft Reset */
- RESET_DE4X5;
-
- /* Restore the GEP */
- if (lp->chipset == DC21140) {
- outl(GEP_INIT, DE4X5_GEP);
- outl(0, DE4X5_GEP);
+ outl(lp->cache.gepc, DE4X5_GEP);
+ outl(lp->cache.gep, DE4X5_GEP);
}
/* Restore CSR6 */
@@ -3670,19 +4405,67 @@
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
int dt;
-
+
/* First, cancel any pending timer events */
del_timer(&lp->timer);
-
+
/* Convert msec to ticks */
dt = (msec * HZ) / 1000;
if (dt==0) dt=1;
-
+
/* Set up timer */
lp->timer.expires = jiffies + dt;
lp->timer.function = fn;
lp->timer.data = data;
add_timer(&lp->timer);
+
+ return;
+}
+
+static void
+yawn(struct device *dev, int state)
+{
+ struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
+ int iobase = dev->base_addr;
+
+ if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
+
+ if(lp->bus == EISA) {
+ switch(state) {
+ case WAKEUP:
+ outb(WAKEUP, PCI_CFPM);
+ de4x5_ms_delay(10);
+ break;
+
+ case SNOOZE:
+ outb(SNOOZE, PCI_CFPM);
+ break;
+
+ case SLEEP:
+ outl(0, DE4X5_SICR);
+ outb(SLEEP, PCI_CFPM);
+ break;
+ }
+ } else {
+ switch(state) {
+ case WAKEUP:
+ pcibios_write_config_byte(lp->bus_num, lp->device << 3,
+ PCI_CFDA_PSM, WAKEUP);
+ de4x5_ms_delay(10);
+ break;
+
+ case SNOOZE:
+ pcibios_write_config_byte(lp->bus_num, lp->device << 3,
+ PCI_CFDA_PSM, SNOOZE);
+ break;
+
+ case SLEEP:
+ outl(0, DE4X5_SICR);
+ pcibios_write_config_byte(lp->bus_num, lp->device << 3,
+ PCI_CFDA_PSM, SLEEP);
+ break;
+ }
+ }
return;
}
@@ -3692,8 +4475,8 @@
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
int i;
-
- if (de4x5_debug > 1) {
+
+ if (de4x5_debug & DEBUG_OPEN) {
printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
printk("\tphysical address: ");
for (i=0;i<6;i++) {
@@ -3730,11 +4513,11 @@
}
}
printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
- printk("Ring size: \nRX: %d\nTX: %d\n",
- (short)lp->rxRingSize,
- (short)lp->txRingSize);
+ printk("Ring size: \nRX: %d\nTX: %d\n",
+ (short)lp->rxRingSize,
+ (short)lp->txRingSize);
}
-
+
return;
}
@@ -3743,8 +4526,8 @@
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
int iobase = dev->base_addr;
-
- if (de4x5_debug > 2) {
+
+ if (de4x5_debug & DEBUG_MII) {
printk("\nMII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
@@ -3761,7 +4544,7 @@
printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
}
}
-
+
return;
}
@@ -3769,18 +4552,18 @@
de4x5_dbg_media(struct device *dev)
{
struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
-
+
if (lp->media != lp->c_media) {
- if (de4x5_debug > 0) {
+ if (de4x5_debug & DEBUG_MEDIA) {
if (lp->chipset != DC21140) {
printk("%s: media is %s\n", dev->name,
(lp->media == NC ? "unconnected!" :
(lp->media == TP ? "TP." :
(lp->media == ANS ? "TP/Nway." :
- (lp->media == BNC ? "BNC." :
- (lp->media == AUI ? "AUI." :
- (lp->media == BNC_AUI ? "BNC/AUI." :
- (lp->media == EXT_SIA ? "EXT SIA." :
+ (lp->media == BNC ? "BNC." :
+ (lp->media == AUI ? "AUI." :
+ (lp->media == BNC_AUI ? "BNC/AUI." :
+ (lp->media == EXT_SIA ? "EXT SIA." :
"???."
))))))));
} else {
@@ -3794,7 +4577,7 @@
}
lp->c_media = lp->media;
}
-
+
return;
}
@@ -3803,10 +4586,12 @@
{
int i;
- if (de4x5_debug > 1) {
- printk("Sub-system Vendor ID: %04x\n", (u_short)*(p->sub_vendor_id));
- printk("Sub-system ID: %04x\n", (u_short)*(p->sub_system_id));
+ if (de4x5_debug & DEBUG_SROM) {
+ printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
+ printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
+ printk("SROM version: %02x\n", (u_char)(p->version));
+ printk("# controllers: %02x\n", (u_char)(p->num_controllers));
printk("Hardware Address: ");
for (i=0;i<ETH_ALEN-1;i++) {
@@ -3827,7 +4612,7 @@
{
int i, j;
- if (de4x5_debug > 2) {
+ if (de4x5_debug & DEBUG_RX) {
printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
(u_char)skb->data[0],
(u_char)skb->data[1],
@@ -3844,7 +4629,7 @@
(u_char)skb->data[12],
(u_char)skb->data[13],
len);
- if (de4x5_debug > 3) {
+ if (de4x5_debug & DEBUG_RX) {
for (j=0; len>0;j+=16, len-=16) {
printk(" %03x: ",j);
for (i=0; i<16 && i<len; i++) {
@@ -3875,7 +4660,7 @@
u16 sval[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
u32 lval[(HASH_TABLE_LEN * ETH_ALEN) >> 2];
} tmp;
-
+
switch(ioc->cmd) {
case DE4X5_GET_HWADDR: /* Get the hardware address */
ioc->len = ETH_ALEN;
@@ -3886,7 +4671,7 @@
tmp.addr[i] = dev->dev_addr[i];
}
copy_to_user(ioc->data, tmp.addr, ioc->len);
-
+
break;
case DE4X5_SET_HWADDR: /* Set the hardware address */
status = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN);
@@ -3903,12 +4688,12 @@
build_setup_frame(dev, PHYS_ADDR_ONLY);
/* Set up the descriptor and give ownership to the card */
while (set_bit(0, (void *)&dev->tbusy) != 0);/* Wait for lock to free*/
- load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
+ load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
SETUP_FRAME_LEN, NULL);
lp->tx_new = (++lp->tx_new) % lp->txRingSize;
outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
dev->tbusy = 0; /* Unlock the TX ring */
-
+
break;
case DE4X5_SET_PROM: /* Set Promiscuous Mode */
if (suser()) {
@@ -3918,7 +4703,7 @@
} else {
status = -EPERM;
}
-
+
break;
case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
if (suser()) {
@@ -3928,19 +4713,19 @@
} else {
status = -EPERM;
}
-
+
break;
case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
printk("%s: Boo!\n", dev->name);
-
+
break;
case DE4X5_GET_MCA: /* Get the multicast address table */
ioc->len = (HASH_TABLE_LEN >> 3);
status = verify_area(VERIFY_WRITE, ioc->data, ioc->len);
if (!status) {
- copy_to_user(ioc->data, lp->setup_frame, ioc->len);
+ copy_to_user(ioc->data, lp->setup_frame, ioc->len);
}
-
+
break;
case DE4X5_SET_MCA: /* Set a multicast address */
if (suser()) {
@@ -3956,7 +4741,7 @@
} else {
status = -EPERM;
}
-
+
break;
case DE4X5_CLR_MCA: /* Clear all multicast addresses */
if (suser()) {
@@ -3965,7 +4750,7 @@
} else {
status = -EPERM;
}
-
+
break;
case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
if (suser()) {
@@ -3975,18 +4760,18 @@
} else {
status = -EPERM;
}
-
+
break;
case DE4X5_GET_STATS: /* Get the driver statistics */
ioc->len = sizeof(lp->pktStats);
status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len);
if (status)
break;
-
+
cli();
- copy_to_user(ioc->data, &lp->pktStats, ioc->len);
+ copy_to_user(ioc->data, &lp->pktStats, ioc->len);
sti();
-
+
break;
case DE4X5_CLR_STATS: /* Zero out the driver statistics */
if (suser()) {
@@ -3996,14 +4781,14 @@
} else {
status = -EPERM;
}
-
+
break;
case DE4X5_GET_OMR: /* Get the OMR Register contents */
tmp.addr[0] = inl(DE4X5_OMR);
if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, 1))) {
copy_to_user(ioc->data, tmp.addr, 1);
}
-
+
break;
case DE4X5_SET_OMR: /* Set the OMR Register contents */
if (suser()) {
@@ -4014,7 +4799,7 @@
} else {
status = -EPERM;
}
-
+
break;
case DE4X5_GET_REG: /* Get the DE4X5 Registers */
j = 0;
@@ -4031,9 +4816,9 @@
copy_to_user(ioc->data, tmp.addr, ioc->len);
}
break;
-
+
#define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
-
+
case DE4X5_DUMP:
j = 0;
tmp.addr[j++] = dev->irq;
@@ -4043,7 +4828,7 @@
tmp.addr[j++] = lp->rxRingSize;
tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
-
+
for (i=0;i<lp->rxRingSize-1;i++){
if (i < 3) {
tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
@@ -4056,7 +4841,7 @@
}
}
tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
-
+
for (i=0;i<lp->rxRingSize-1;i++){
if (i < 3) {
tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
@@ -4069,14 +4854,14 @@
}
}
tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
-
+
for (i=0;i<lp->rxRingSize;i++){
tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
}
for (i=0;i<lp->txRingSize;i++){
tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
}
-
+
tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
@@ -4085,18 +4870,18 @@
tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
- tmp.lval[j>>2] = lp->chipset; j+=4;
+ tmp.lval[j>>2] = lp->chipset; j+=4;
if (lp->chipset == DC21140) {
tmp.lval[j>>2] = inl(DE4X5_GEP); j+=4;
} else {
tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
- tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
+ tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
}
- tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
- if (lp->phy[lp->active].id) {
- tmp.lval[j>>2] = lp->active; j+=4;
+ tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
+ if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
+ tmp.lval[j>>2] = lp->active; j+=4;
tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
@@ -4113,20 +4898,20 @@
tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
}
}
-
+
tmp.addr[j++] = lp->txRingSize;
tmp.addr[j++] = dev->tbusy;
-
+
ioc->len = j;
if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len))) {
copy_to_user(ioc->data, tmp.addr, ioc->len);
}
-
+
break;
default:
status = -EOPNOTSUPP;
}
-
+
return status;
}
@@ -4135,81 +4920,33 @@
** Note now that module autoprobing is allowed under EISA and PCI. The
** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
** to "do the right thing".
-**
-** The module autoprobe will only load one instance of the driver and
-** hardware.
*/
-static char devicename[9] = { 0, };
-static struct device thisDE4X5 = {
- devicename, /* device name inserted by /linux/drivers/net/net_init.c */
- 0, 0, 0, 0,
- 0, 0, /* I/O address, IRQ */
- 0, 0, 0, NULL, de4x5_probe };
-
-static int io=0x0; /* EDIT THESE LINES FOR YOUR CONFIGURATION */
-MODULE_PARM(io, "i");
+#define LP(a) ((struct de4x5_private *)(a))
+static struct device *mdev = NULL;
+static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
int
init_module(void)
{
- struct device *p = (struct device *)&thisDE4X5;
+ struct device *p;
- thisDE4X5.base_addr = io; /* Now autoprobe the module */
- thisDE4X5.irq = 0;
+ if ((mdev = insert_device(NULL, io, de4x5_probe)) == NULL)
+ return -ENOMEM;
- for (; p!=NULL; p=p->next) {
+ for (p = mdev; p != NULL; p = LP(p->priv)->next_module) {
if (register_netdev(p) != 0)
return -EIO;
}
- io=0;
+
return 0;
}
void
cleanup_module(void)
{
- struct de4x5_private *lp = (struct de4x5_private *) thisDE4X5.priv;
- struct device *p = (struct device *)&thisDE4X5;
- int keep_loaded = 0;
-
- for (; p!=NULL; p=p->next) {
- keep_loaded += (p->flags & IFF_UP); /* Is an interface up? */
- }
-
- if (keep_loaded) {
- printk("de4x5: Cannot unload modules - %d interface%s%s still active.\n",
- keep_loaded, (keep_loaded>1 ? "s ": " "),
- (keep_loaded>1 ? "are": "is"));
- return;
- }
-
- for (p=thisDE4X5.next; p!=NULL; p=p->next) {
- if (p->priv) { /* Private area allocated? */
- struct de4x5_private *lp = (struct de4x5_private *)p->priv;
- if (lp->cache.buf) { /* MAC buffers allocated? */
- kfree(lp->cache.buf); /* Free the MAC buffers */
- }
- release_region(p->base_addr, (lp->bus == PCI ?
- DE4X5_PCI_TOTAL_SIZE :
- DE4X5_EISA_TOTAL_SIZE));
- kfree(lp->cache.priv); /* Free the private area */
- }
- unregister_netdev(p);
- kfree(p); /* Free the device structure */
- }
-
- if (thisDE4X5.priv) {
- if (lp->cache.buf) { /* Are MAC buffers allocated */
- kfree(lp->cache.buf);
- }
- release_region(thisDE4X5.base_addr,
- (lp->bus == PCI ?
- DE4X5_PCI_TOTAL_SIZE :
- DE4X5_EISA_TOTAL_SIZE));
- kfree(lp->cache.priv);
- thisDE4X5.priv = NULL;
+ while (mdev != NULL) {
+ mdev = unlink_modules(mdev);
}
- unregister_netdev(&thisDE4X5);
return;
}
FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen, slshen@lbl.gov