patch-2.4.20 linux-2.4.20/include/asm-parisc/cache.h

• Lines: 98
• Date: Thu Nov 28 15:53:15 2002
• Orig file: linux-2.4.19/include/asm-parisc/cache.h
• Orig date: Wed Dec 6 11:46:39 2000

diff -urN linux-2.4.19/include/asm-parisc/cache.h linux-2.4.20/include/asm-parisc/cache.h
@@ -5,27 +5,18 @@
 #ifndef __ARCH_PARISC_CACHE_H
 #define __ARCH_PARISC_CACHE_H
 
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
 /*
-** XXX FIXME : L1_CACHE_BYTES (cacheline size) should be a boot time thing.
-** 
-** 32-bit on PA2.0 is not covered well by the #ifdef __LP64__ below.
-** PA2.0 processors have 64-byte cachelines.
-**
-** The issue is mostly cacheline ping-ponging on SMP boxes.
-** To avoid this, code should define stuff to be per CPU on cacheline
-** aligned boundaries. This can make a 2x or more difference in perf
-** depending on how badly the thrashing is.
-**
-** We don't need to worry about I/O since all PA2.0 boxes (except T600)
-** are I/O coherent. That means flushing less than you needed to generally
-** doesn't matter - the I/O MMU will read/modify/write the cacheline.
-**
-** (Digression: it is possible to program I/O MMU's to not first read
-** a cacheline for inbound data - ie just grab ownership and start writing.
-** While it improves I/O throughput, you gotta know the device driver
-** is well behaved and can deal with the issues.)
-*/
-#if defined(__LP64__)
+ * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have
+ * 32-byte cachelines.  The default configuration is not for SMP anyway,
+ * so if you're building for SMP, you should select the appropriate
+ * processor type.  There is a potential livelock danger when running
+ * a machine with this value set too small, but it's more probable you'll
+ * just ruin performance.
+ */
+#ifdef CONFIG_PA20
 #define L1_CACHE_BYTES 64
 #else
 #define L1_CACHE_BYTES 32
@@ -37,22 +28,47 @@
 
 #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
 
-extern void init_cache(void);		/* initializes cache-flushing */
-extern void flush_data_cache(void);	/* flushes data-cache only */
-extern void flush_instruction_cache(void);/* flushes code-cache only */
-extern void flush_all_caches(void);	/* flushes code and data-cache */
+extern void flush_data_cache_local(void);  /* flushes local data-cache only */
+extern void flush_instruction_cache_local(void); /* flushes local code-cache only */
+#ifdef CONFIG_SMP
+extern void flush_data_cache(void); /* flushes data-cache only (all processors) */
+#else
+#define flush_data_cache flush_data_cache_local
+#define flush_instruction_cache flush_instruction_cache_local
+#endif
 
+extern void cache_init(void);		/* initializes cache-flushing */
+extern void flush_all_caches(void);     /* flush everything (tlb & cache) */
 extern int get_cache_info(char *);
-
+extern void flush_user_icache_range_asm(unsigned long, unsigned long);
+extern void flush_kernel_icache_range_asm(unsigned long, unsigned long);
+extern void flush_user_dcache_range_asm(unsigned long, unsigned long);
+extern void flush_kernel_dcache_range_asm(unsigned long, unsigned long);
+extern void flush_kernel_dcache_page(void *);
+extern void flush_kernel_icache_page(void *);
+extern void disable_sr_hashing(void);   /* turns off space register hashing */
+extern void disable_sr_hashing_asm(int); /* low level support for above */
+extern void free_sid(unsigned long);
+unsigned long alloc_sid(void);
+
+struct seq_file;
+extern void show_cache_info(struct seq_file *m);
+
+extern int split_tlb;
+extern int dcache_stride;
+extern int icache_stride;
 extern struct pdc_cache_info cache_info;
 
-#define fdce(addr) asm volatile("fdce 0(%0)" : : "r" (addr))
-#define fice(addr) asm volatile("fice 0(%%sr1,%0)" : : "r" (addr))
-
-#define pdtlbe(addr) asm volatile("pdtlbe 0(%%sr1,%0)" : : "r" (addr))
+#define pdtlb(addr)         asm volatile("pdtlb 0(%%sr1,%0)" : : "r" (addr));
+#define pitlb(addr)         asm volatile("pitlb 0(%%sr1,%0)" : : "r" (addr));
 #define pdtlb_kernel(addr)  asm volatile("pdtlb 0(%0)" : : "r" (addr));
-#define pitlbe(addr) asm volatile("pitlbe 0(%%sr1,%0)" : : "r" (addr))
 
-#define kernel_fdc(addr) asm volatile("fdc 0(%%sr0, %0)" : : "r" (addr))
+#endif /* ! __ASSEMBLY__ */
+
+/* Classes of processor wrt: disabling space register hashing */
+
+#define SRHASH_PCXST    0   /* pcxs, pcxt, pcxt_ */
+#define SRHASH_PCXL     1   /* pcxl */
+#define SRHASH_PA20     2   /* pcxu, pcxu_, pcxw, pcxw_ */
 
 #endif