****library: "samples"
version: 6.05bp
aids: 14
aidname: user
aidname: io
aidname: compaction
aidname: pla
aidname: routing
aidname: silicon-compiler
aidname: vhdl-compiler
aidname: compensation
aidname: logeffort
aidname: network
aidname: drc
aidname: erc
aidname: simulation
aidname: project
userbits: 6
techcount: 16
techname: generic lambda: 2000
techname: nmos lambda: 4000
techname: cmos lambda: 4000
techname: mocmos lambda: 400
variables: 1
TECH_last_state[01,00/00]: 8
techname: mocmosold lambda: 2000
techname: mocmossub lambda: 400
variables: 1
TECH_last_state[01,00/00]: 8
techname: bicmos lambda: 2000
techname: rcmos lambda: 2000
techname: cmosdodn lambda: 2000
techname: bipolar lambda: 4000
techname: schematic lambda: 4000
techname: fpga lambda: 2000
techname: pcb lambda: 2540000
techname: artwork lambda: 4000
variables: 1
TECH_last_state[01,00/00]: 0
techname: gem lambda: 2000
techname: efido lambda: 20000
view: schematic-page-2{p2}
view: schematic-page-1{p1}
view: layout{lay}
view: schematic{sch}
view: icon{ic}
view: documentation{doc}
view: compensated{comp}
view: skeleton{sk}
view: Verilog{ver}
view: VHDL{vhdl}
view: netlist{net}
view: netlist-als-format{net-als}
view: netlist-quisc-format{net-quisc}
view: netlist-silos-format{net-silos}
view: netlist-rsim-format{net-rsim}
view: netlist-netlisp-format{net-netlisp}
view: simulation-snapshot{sim}
view: unknown{}
cellcount: 31
maincell: 6
***cell: 0
name: tech-nMOSPullup{lay}
version: 1
creationdate: 0
revisiondate: 612141470
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celldone: tech-nMOSPullup
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name: tech-nMOS{lay}
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revisiondate: 976904012
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celldone: tech-Artwork
***cell: 3
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GEM_element[04,00/00]: "Prepare Site"
GEM_event1[04,00/00]: "Access"
GEM_event2[04,00/00]: "Demolish"
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GEM_event4[04,00/00]: " "
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GEM_event1[04,00/00]: "Electricity"
GEM_event2[04,00/00]: "Plumbing"
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GEM_event3[04,00/00]: "Exterior Wall"
GEM_event4[04,00/00]: "Painting"
GEM_element[04,00/00]: "Finishing"
GEM_event1[04,00/00]: "Drywall"
GEM_event2[04,00/00]: "Roofing"
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celldone: tech-GEM
***cell: 6
name: tech-MOSISCMOS{lay}
version: 1
creationdate: 901321855
revisiondate: 1007930129
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aadirty: 6638
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***cell: 11
name: tech-PCB
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creationdate: 0
revisiondate: 975718207
lowx: -123444000 highx: 188336000 lowy: -132057000 highy: 104775000
aadirty: 6638
userbits: 827392
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type: pcb:Signal-2-Pin
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type: pcb:Signal-2-Pin
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type: pcb:Signal-2-Pin
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type: pcb:Signal-2-Pin
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arc: 8
arc: 9
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type: pcb:Signal-4-Pin
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arc: 12
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arc: 16
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type: pcb:Signal-3-Pin
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arc: 16
arc: 17
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type: pcb:Signal-8-Pin
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arc: 20
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arc: 21
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arc: 22
arc: 23
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arc: 24
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arc: 26
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arc: 28
arc: 29
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arc: 30
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arc: 32
arc: 33
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type: pcb:Signal-8-Pin
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type: pcb:Signal-8-Pin
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arc: 38
arc: 39
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type: pcb:Signal-8-Pin
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arc: 41
arc: 42
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type: pcb:Signal-8-Pin
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arc: 44
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type: pcb:Signal-8-Pin
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type: pcb:Signal-8-Pin
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arc: 44
arc: 46
arc: 47
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type: pcb:Signal-8-Pin
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arc: 49
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type: pcb:Signal-8-Pin
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arc: 49
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type: pcb:Signal-1-Pin
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arc: 51
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type: pcb:Signal-1-Pin
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type: pcb:Signal-1-Pin
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type: pcb:Signal-1-Pin
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type: pcb:Signal-1-Pin
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arc: 55
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type: pcb:Signal-1-Pin
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type: pcb:Signal-1-Pin
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arc: 58
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type: pcb:Signal-1-Pin
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arc: 60
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type: pcb:Signal-1-Pin
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arc: 63
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arc: 65
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type: pcb:Signal-1-Pin
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arc: 65
arc: 66
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arc: 68
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type: pcb:Signal-1-Pin
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arc: 69
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type: pcb:Signal-1-Pin
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arc: 71
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arc: 72
arc: 73
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arc: 74
arc: 75
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arc: 76
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arc: 77
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arc: 78
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arc: 80
**node: 60
type: [7]
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userbits: 7168
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*port: -CLK23/1
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*port: D22/1
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type: [7]
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userbits: 7168
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*port: -CLK13/0
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*port: -Q16/0
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*port: Q25/1
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*port: -CLK23/1
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*port: D22/1
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*port: TISP1/0
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*port: TISP2/1
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*port: TISP3/1
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SCHEM_resistance[0104,0100000001/0400]: "40K"
*port: a
arc: 20
*port: b
arc: 63
**node: 14
type: schematic:Resistor
lowx: 100800 highx: 124800 lowy: 82400 highy: 86400
rotation: 900 transpose: 0
userbits: 3072
variables: 1
SCHEM_resistance[0104,0100000001/0400]: " 10K"
*port: a
arc: 18
*port: b
arc: 62
**node: 15
type: schematic:Wire_Pin
lowx: 111800 highx: 113800 lowy: 175400 highy: 177400
rotation: 0 transpose: 0
userbits: 7168
*port: wire
arc: 6
arc: 7
**node: 16
type: schematic:Wire_Pin
lowx: 87800 highx: 89800 lowy: 175400 highy: 177400
rotation: 0 transpose: 0
userbits: 7168
*port: wire
arc: 7
arc: 8
arc: 9
**node: 17
type: schematic:Wire_Pin
lowx: 63800 highx: 65800 lowy: 175400 highy: 177400
rotation: 0 transpose: 0
userbits: 7168
*port: wire
arc: 9
arc: 10
arc: 11
**node: 18
type: schematic:Wire_Pin
lowx: 39800 highx: 41800 lowy: 175400 highy: 177400
rotation: 0 transpose: 0
userbits: 7168
*port: wire
arc: 11
arc: 12
arc: 85
**node: 19
type: schematic:Wire_Pin
lowx: 15800 highx: 17800 lowy: 59400 highy: 61400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 17
arc: 23
**node: 20
type: schematic:Wire_Pin
lowx: 111800 highx: 113800 lowy: 59400 highy: 61400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 18
arc: 19
arc: 88
**node: 21
type: schematic:Wire_Pin
lowx: 87800 highx: 89800 lowy: 59400 highy: 61400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 19
arc: 20
arc: 21
**node: 22
type: schematic:Wire_Pin
lowx: 63800 highx: 65800 lowy: 59400 highy: 61400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 21
arc: 22
arc: 24
**node: 23
type: schematic:Wire_Pin
lowx: 39800 highx: 41800 lowy: 59400 highy: 61400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 23
arc: 24
arc: 25
**node: 24
type: schematic:Transistor
lowx: 196800 highx: 212800 lowy: 152400 highy: 168400
rotation: 1800 transpose: 1
userbits: 396288
*port: g
arc: 43
arc: 45
*port: s
arc: 55
*port: d
arc: 44
**node: 25
type: schematic:Transistor
lowx: 220800 highx: 236800 lowy: 152400 highy: 168400
rotation: 1800 transpose: 1
userbits: 396288
*port: g
arc: 33
arc: 43
*port: s
arc: 46
*port: d
arc: 40
**node: 26
type: schematic:Transistor
lowx: 244800 highx: 260800 lowy: 152400 highy: 168400
rotation: 1800 transpose: 1
userbits: 396288
*port: g
arc: 33
arc: 36
*port: s
arc: 47
*port: d
arc: 34
**node: 27
type: schematic:Resistor
lowx: 184800 highx: 208800 lowy: 74400 highy: 78400
rotation: 900 transpose: 0
userbits: 68608
variables: 1
SCHEM_resistance[0104,0100000001/0400]: "15K"
*port: a
arc: 92
*port: b
arc: 51
**node: 28
type: schematic:Resistor
lowx: 208800 highx: 232800 lowy: 74400 highy: 78400
rotation: 900 transpose: 0
userbits: 3072
variables: 1
SCHEM_resistance[0104,0100000001/0400]: " 10K"
*port: a
arc: 32
*port: b
arc: 46
**node: 29
type: schematic:Resistor
lowx: 232800 highx: 256800 lowy: 74400 highy: 78400
rotation: 900 transpose: 0
userbits: 3072
variables: 1
SCHEM_resistance[0104,0100000001/0400]: " 20K"
*port: a
arc: 31
*port: b
arc: 47
**node: 30
type: schematic:Transistor
lowx: 268800 highx: 284800 lowy: 152400 highy: 168400
rotation: 1800 transpose: 1
userbits: 396288
*port: g
arc: 36
arc: 37
*port: s
arc: 48
*port: d
arc: 38
**node: 31
type: schematic:Transistor
lowx: 292800 highx: 308800 lowy: 152400 highy: 168400
rotation: 1800 transpose: 1
userbits: 396288
*port: g
arc: 37
*port: s
arc: 49
*port: d
arc: 39
**node: 32
type: schematic:Resistor
lowx: 256800 highx: 280800 lowy: 74400 highy: 78400
rotation: 900 transpose: 0
userbits: 3072
variables: 1
SCHEM_resistance[0104,0100000001/0400]: "40K"
*port: a
arc: 26
*port: b
arc: 48
**node: 33
type: schematic:Resistor
lowx: 280800 highx: 304800 lowy: 74400 highy: 78400
rotation: 900 transpose: 0
userbits: 3072
variables: 1
SCHEM_resistance[0104,0100000001/0400]: " 10K"
*port: a
arc: 28
*port: b
arc: 49
**node: 34
type: schematic:Wire_Pin
lowx: 291800 highx: 293800 lowy: 175400 highy: 177400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 35
arc: 39
**node: 35
type: schematic:Wire_Pin
lowx: 267800 highx: 269800 lowy: 175400 highy: 177400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 35
arc: 38
arc: 42
**node: 36
type: schematic:Wire_Pin
lowx: 243800 highx: 245800 lowy: 175400 highy: 177400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 34
arc: 41
arc: 42
**node: 37
type: schematic:Wire_Pin
lowx: 219800 highx: 221800 lowy: 175400 highy: 177400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 40
arc: 41
arc: 67
**node: 38
type: schematic:Wire_Pin
lowx: 195800 highx: 197800 lowy: 191400 highy: 193400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 44
arc: 57
**node: 39
type: schematic:Wire_Pin
lowx: 291800 highx: 293800 lowy: 59400 highy: 61400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 27
arc: 28
**node: 40
type: schematic:Wire_Pin
lowx: 267800 highx: 269800 lowy: 59400 highy: 61400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 26
arc: 27
arc: 30
**node: 41
type: schematic:Wire_Pin
lowx: 243800 highx: 245800 lowy: 59400 highy: 61400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 29
arc: 30
arc: 31
**node: 42
type: schematic:Wire_Pin
lowx: 219800 highx: 221800 lowy: 59400 highy: 61400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 29
arc: 32
arc: 91
**node: 43
type: schematic:Resistor
lowx: 184800 highx: 208800 lowy: 106400 highy: 110400
rotation: 900 transpose: 0
userbits: 68608
variables: 1
SCHEM_resistance[0104,0100000001/0400]: "270"
*port: a
arc: 50
*port: b
arc: 54
**node: 44
type: schematic:Wire_Pin
lowx: 135800 highx: 137800 lowy: 91400 highy: 93400
rotation: 0 transpose: 0
userbits: 68608
*port: wire
arc: 52
arc: 95
**node: 45
type: schematic:Wire_Pin
lowx: 195800 highx: 197800 lowy: 91400 highy: 93400
rotation: 0 transpose: 0
userbits: 68608
*port: wire
arc: 50
arc: 51
arc: 52
**node: 46
type: schematic:Resistor
lowx: 144800 highx: 168800 lowy: 134400 highy: 138400
rotation: 900 transpose: 0
userbits: 68608
variables: 1
SCHEM_resistance[0104,020100000002/0400]: " 390"
*port: a
arc: 53
*port: b
arc: 60
**node: 47
type: schematic:Wire_Pin
lowx: 155800 highx: 157800 lowy: 123400 highy: 125400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 53
arc: 56
**node: 48
type: schematic:Wire_Pin
lowx: 195800 highx: 197800 lowy: 123400 highy: 125400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 54
arc: 55
arc: 56
**node: 49
type: schematic:Resistor
lowx: 144800 highx: 168800 lowy: 170400 highy: 174400
rotation: 900 transpose: 0
userbits: 68608
variables: 1
SCHEM_resistance[0104,020100000002/0400]: "20K"
*port: a
arc: 59
*port: b
arc: 58
**node: 50
type: schematic:Wire_Pin
lowx: 155800 highx: 157800 lowy: 191400 highy: 193400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 57
arc: 58
arc: 87
**node: 51
type: schematic:Wire_Pin
lowx: 135800 highx: 137800 lowy: 151400 highy: 153400
rotation: 0 transpose: 0
userbits: 68608
*port: wire
arc: 61
arc: 94
**node: 52
type: schematic:Wire_Pin
lowx: 155800 highx: 157800 lowy: 151400 highy: 153400
rotation: 0 transpose: 0
userbits: 68608
*port: wire
arc: 59
arc: 60
arc: 61
**node: 53
type: schematic:Wire_Pin
lowx: 219800 highx: 221800 lowy: 211400 highy: 213400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 66
arc: 68
arc: 74
**node: 54
type: schematic:Resistor
lowx: 188800 highx: 212800 lowy: 210400 highy: 214400
rotation: 0 transpose: 0
userbits: 7168
variables: 1
SCHEM_resistance[0104,0100000001/0400]: "14.0625K"
*port: a
arc: 83
*port: b
arc: 66
**node: 55
type: schematic:Resistor
lowx: 192800 highx: 216800 lowy: 230400 highy: 234400
rotation: 0 transpose: 0
userbits: 7168
variables: 2
NODE_name[0104,0100000001/0400]: "TR3"
SCHEM_resistance[0104,00/0400]: " "
*port: a
arc: 82
*port: b
arc: 71
**node: 56
type: schematic:Resistor
lowx: 248800 highx: 272800 lowy: 230400 highy: 234400
rotation: 0 transpose: 0
userbits: 3072
variables: 2
NODE_name[0104,0100000001/0400]: "TR4"
SCHEM_resistance[0104,00/0400]: " "
*port: a
arc: 70
*port: b
arc: 78
**node: 57
type: schematic:Wire_Pin
lowx: 235800 highx: 237800 lowy: 195400 highy: 197400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 69
arc: 72
**node: 58
type: schematic:Wire_Pin
lowx: 219800 highx: 221800 lowy: 195400 highy: 197400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 67
arc: 68
arc: 69
**node: 59
type: schematic:Wire_Pin
lowx: 235800 highx: 237800 lowy: 231400 highy: 233400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 70
arc: 71
arc: 72
**node: 60
type: schematic:Resistor
lowx: 256800 highx: 280800 lowy: 194400 highy: 198400
rotation: 0 transpose: 0
userbits: 3072
variables: 1
SCHEM_resistance[0104,0100000001/0400]: " 1K"
*port: a
arc: 73
*port: b
arc: 80
**node: 61
type: schematic:Wire_Pin
lowx: 251800 highx: 253800 lowy: 195400 highy: 197400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 73
arc: 75
**node: 62
type: schematic:Wire_Pin
lowx: 251800 highx: 253800 lowy: 211400 highy: 213400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 74
arc: 75
arc: 76
**node: 63
type: schematic:Resistor
lowx: 264800 highx: 288800 lowy: 210400 highy: 214400
rotation: 0 transpose: 0
userbits: 3072
variables: 1
SCHEM_resistance[0104,0100000001/0400]: "14.0625K"
*port: a
arc: 76
*port: b
arc: 77
**node: 64
type: schematic:Wire_Pin
lowx: 307800 highx: 309800 lowy: 211400 highy: 213400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 77
**node: 65
type: schematic:Wire_Pin
lowx: 295800 highx: 297800 lowy: 231400 highy: 233400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 78
arc: 79
**node: 66
type: schematic:Wire_Pin
lowx: 295800 highx: 297800 lowy: 195400 highy: 197400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 79
arc: 80
arc: 81
**node: 67
type: schematic:Substrate
lowx: 308800 highx: 316800 lowy: 192400 highy: 200400
rotation: 900 transpose: 0
userbits: 3072
*port: substrate
arc: 81
**node: 68
type: schematic:Wire_Pin
lowx: 179800 highx: 181800 lowy: 231400 highy: 233400
rotation: 0 transpose: 0
userbits: 7168
*port: wire
arc: 82
arc: 84
**node: 69
type: schematic:Wire_Pin
lowx: 179800 highx: 181800 lowy: 211400 highy: 213400
rotation: 0 transpose: 0
userbits: 7168
*port: wire
arc: 83
arc: 84
arc: 86
**node: 70
type: schematic:Wire_Pin
lowx: 39800 highx: 41800 lowy: 211400 highy: 213400
rotation: 0 transpose: 0
userbits: 7168
*port: wire
arc: 85
arc: 86
**node: 71
type: schematic:Power
lowx: 150800 highx: 162800 lowy: 198400 highy: 210400
rotation: 0 transpose: 0
userbits: 3072
*port: pwr
arc: 87
**node: 72
type: schematic:Ground
lowx: 134800 highx: 146800 lowy: 36400 highy: 52400
rotation: 0 transpose: 0
userbits: 3072
*port: gnd
arc: 89
**node: 73
type: schematic:Wire_Pin
lowx: 139800 highx: 141800 lowy: 59400 highy: 61400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 88
arc: 89
arc: 90
**node: 74
type: schematic:Wire_Pin
lowx: 195800 highx: 197800 lowy: 59400 highy: 61400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 90
arc: 91
arc: 92
**node: 75
type: artwork:Opened-Dashed-Polygon
lowx: 32800 highx: 128800 lowy: 140400 highy: 188400
rotation: 0 transpose: 0
userbits: 3072
variables: 1
trace[012201,00/00]: [-48000,24000,48000,24000,48000,-24000,-48000,-24000,-48000,24000]
**node: 76
type: artwork:Opened-Dashed-Polygon
lowx: 212800 highx: 308800 lowy: 140400 highy: 188400
rotation: 0 transpose: 0
userbits: 3072
variables: 1
trace[012201,00/00]: [-48000,24000,48000,24000,48000,-24000,-48000,-24000,-48000,24000]
**node: 77
type: schematic:Wire_Pin
lowx: 15800 highx: 17800 lowy: 187400 highy: 189400
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 93
**node: 78
type: schematic:Off-Page
lowx: 128800 highx: 144800 lowy: 108400 highy: 116400
rotation: 2700 transpose: 0
userbits: 68608
*port: a
arc: 94
*port: y
arc: 95
**arc: 0
type: schematic:wire
width: 0 length: 20000
userbits: 813697858
*end: 0
node: 1
nodeport: y
xpos: 16800 ypos: 132400
*end: 1
node: 0
nodeport: s
xpos: 16800 ypos: 152400
**arc: 1
type: schematic:wire
width: 0 length: 20000
userbits: 813697858
*end: 0
node: 3
nodeport: y
xpos: 40800 ypos: 132400
*end: 1
node: 2
nodeport: s
xpos: 40800 ypos: 152400
**arc: 2
type: schematic:wire
width: 0 length: 20000
userbits: 813697858
*end: 0
node: 5
nodeport: y
xpos: 64800 ypos: 132400
*end: 1
node: 4
nodeport: s
xpos: 64800 ypos: 152400
**arc: 3
type: schematic:wire
width: 0 length: 24000
userbits: 813697858
*end: 0
node: 6
nodeport: b
xpos: 16800 ypos: 92400
*end: 1
node: 1
nodeport: a
xpos: 16800 ypos: 116400
**arc: 4
type: schematic:wire
width: 0 length: 20000
userbits: 813697858
*end: 0
node: 12
nodeport: y
xpos: 112800 ypos: 132400
*end: 1
node: 11
nodeport: s
xpos: 112800 ypos: 152400
**arc: 5
type: schematic:wire
width: 0 length: 20000
userbits: 813697858
*end: 0
node: 10
nodeport: y
xpos: 88800 ypos: 132400
*end: 1
node: 9
nodeport: s
xpos: 88800 ypos: 152400
**arc: 6
type: schematic:wire
width: 0 length: 8000
userbits: 1887439682
*end: 0
node: 11
nodeport: d
xpos: 112800 ypos: 168400
*end: 1
node: 15
nodeport: wire
xpos: 112800 ypos: 176400
**arc: 7
type: schematic:wire
width: 0 length: 24000
userbits: 1904219778
*end: 0
node: 15
nodeport: wire
xpos: 112800 ypos: 176400
*end: 1
node: 16
nodeport: wire
xpos: 88800 ypos: 176400
**arc: 8
type: schematic:wire
width: 0 length: 8000
userbits: 1887439682
*end: 0
node: 9
nodeport: d
xpos: 88800 ypos: 168400
*end: 1
node: 16
nodeport: wire
xpos: 88800 ypos: 176400
**arc: 9
type: schematic:wire
width: 0 length: 24000
userbits: 1887442562
*end: 0
node: 16
nodeport: wire
xpos: 88800 ypos: 176400
*end: 1
node: 17
nodeport: wire
xpos: 64800 ypos: 176400
**arc: 10
type: schematic:wire
width: 0 length: 8000
userbits: 1887439682
*end: 0
node: 4
nodeport: d
xpos: 64800 ypos: 168400
*end: 1
node: 17
nodeport: wire
xpos: 64800 ypos: 176400
**arc: 11
type: schematic:wire
width: 0 length: 24000
userbits: 1887442562
*end: 0
node: 17
nodeport: wire
xpos: 64800 ypos: 176400
*end: 1
node: 18
nodeport: wire
xpos: 40800 ypos: 176400
**arc: 12
type: schematic:wire
width: 0 length: 8000
userbits: 1887439682
*end: 0
node: 2
nodeport: d
xpos: 40800 ypos: 168400
*end: 1
node: 18
nodeport: wire
xpos: 40800 ypos: 176400
**arc: 13
type: schematic:wire
width: 0 length: 24000
userbits: 813700738
*end: 0
node: 11
nodeport: g
xpos: 124800 ypos: 160400
*end: 1
node: 9
nodeport: g
xpos: 100800 ypos: 160400
**arc: 14
type: schematic:wire
width: 0 length: 24000
userbits: 813700738
*end: 0
node: 9
nodeport: g
xpos: 100800 ypos: 160400
*end: 1
node: 4
nodeport: g
xpos: 76800 ypos: 160400
**arc: 15
type: schematic:wire
width: 0 length: 24000
userbits: 813700738
*end: 0
node: 4
nodeport: g
xpos: 76800 ypos: 160400
*end: 1
node: 2
nodeport: g
xpos: 52800 ypos: 160400
**arc: 16
type: schematic:wire
width: 0 length: 24000
userbits: 813700738
*end: 0
node: 2
nodeport: g
xpos: 52800 ypos: 160400
*end: 1
node: 0
nodeport: g
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**arc: 17
type: schematic:wire
width: 0 length: 16000
userbits: 813703618
*end: 0
node: 6
nodeport: a
xpos: 16800 ypos: 76400
*end: 1
node: 19
nodeport: wire
xpos: 16800 ypos: 60400
**arc: 18
type: schematic:wire
width: 0 length: 16000
userbits: 813703618
*end: 0
node: 14
nodeport: a
xpos: 112800 ypos: 76400
*end: 1
node: 20
nodeport: wire
xpos: 112800 ypos: 60400
**arc: 19
type: schematic:wire
width: 0 length: 24000
userbits: 813694978
*end: 0
node: 21
nodeport: wire
xpos: 88800 ypos: 60400
*end: 1
node: 20
nodeport: wire
xpos: 112800 ypos: 60400
**arc: 20
type: schematic:wire
width: 0 length: 16000
userbits: 813703618
*end: 0
node: 13
nodeport: a
xpos: 88800 ypos: 76400
*end: 1
node: 21
nodeport: wire
xpos: 88800 ypos: 60400
**arc: 21
type: schematic:wire
width: 0 length: 24000
userbits: 813694978
*end: 0
node: 22
nodeport: wire
xpos: 64800 ypos: 60400
*end: 1
node: 21
nodeport: wire
xpos: 88800 ypos: 60400
**arc: 22
type: schematic:wire
width: 0 length: 16000
userbits: 813703618
*end: 0
node: 8
nodeport: a
xpos: 64800 ypos: 76400
*end: 1
node: 22
nodeport: wire
xpos: 64800 ypos: 60400
**arc: 23
type: schematic:wire
width: 0 length: 24000
userbits: 813694978
*end: 0
node: 19
nodeport: wire
xpos: 16800 ypos: 60400
*end: 1
node: 23
nodeport: wire
xpos: 40800 ypos: 60400
**arc: 24
type: schematic:wire
width: 0 length: 24000
userbits: 813694978
*end: 0
node: 23
nodeport: wire
xpos: 40800 ypos: 60400
*end: 1
node: 22
nodeport: wire
xpos: 64800 ypos: 60400
**arc: 25
type: schematic:wire
width: 0 length: 16000
userbits: 813703618
*end: 0
node: 7
nodeport: a
xpos: 40800 ypos: 76400
*end: 1
node: 23
nodeport: wire
xpos: 40800 ypos: 60400
**arc: 26
type: schematic:wire
width: 0 length: 8000
userbits: 813703618
*end: 0
node: 32
nodeport: a
xpos: 268800 ypos: 68400
*end: 1
node: 40
nodeport: wire
xpos: 268800 ypos: 60400
**arc: 27
type: schematic:wire
width: 0 length: 24000
userbits: 813694978
*end: 0
node: 40
nodeport: wire
xpos: 268800 ypos: 60400
*end: 1
node: 39
nodeport: wire
xpos: 292800 ypos: 60400
**arc: 28
type: schematic:wire
width: 0 length: 8000
userbits: 813703618
*end: 0
node: 33
nodeport: a
xpos: 292800 ypos: 68400
*end: 1
node: 39
nodeport: wire
xpos: 292800 ypos: 60400
**arc: 29
type: schematic:wire
width: 0 length: 24000
userbits: 813694978
*end: 0
node: 42
nodeport: wire
xpos: 220800 ypos: 60400
*end: 1
node: 41
nodeport: wire
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 40
arc: 41
**node: 26
type: schematic:Wire_Pin
lowx: 71000 highx: 73000 lowy: -301000 highy: -299000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 37
arc: 42
arc: 44
**node: 27
type: schematic:Wire_Pin
lowx: 159000 highx: 161000 lowy: -301000 highy: -299000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 47
exported: 8
**node: 28
type: schematic:Wire_Pin
lowx: 147000 highx: 149000 lowy: -301000 highy: -299000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 24
arc: 43
arc: 47
**node: 29
type: schematic:Wire_Pin
lowx: -157000 highx: -155000 lowy: -301000 highy: -299000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 46
exported: 4
**node: 30
type: schematic:Wire_Pin
lowx: 11000 highx: 13000 lowy: -293000 highy: -291000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 7
arc: 48
**node: 31
type: schematic:Wire_Pin
lowx: -41000 highx: -39000 lowy: -293000 highy: -291000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 39
arc: 49
arc: 50
**node: 32
type: schematic:And
lowx: -24000 highx: 8000 lowy: -284000 highy: -260000
rotation: 0 transpose: 0
userbits: 3072
*port: a
arc: 51
arc: 54
*port: y
arc: 53
**node: 33
type: schematic:Wire_Pin
lowx: -49000 highx: -47000 lowy: -281000 highy: -279000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 31
arc: 51
arc: 52
**node: 34
type: schematic:Wire_Pin
lowx: 11000 highx: 13000 lowy: -273000 highy: -271000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 48
arc: 53
**node: 35
type: schematic:Wire_Pin
lowx: -33000 highx: -31000 lowy: -265000 highy: -263000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 54
arc: 55
**node: 36
type: schematic:Wire_Pin
lowx: -33000 highx: -31000 lowy: -253000 highy: -251000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 55
arc: 57
arc: 58
**node: 37
type: schematic:Wire_Pin
lowx: 147000 highx: 149000 lowy: -253000 highy: -251000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 56
arc: 57
**node: 38
type: schematic:And
lowx: -24000 highx: 8000 lowy: -244000 highy: -220000
rotation: 0 transpose: 0
userbits: 7168
*port: a
arc: 59
arc: 61
arc: 64
*port: y
arc: 60
**node: 39
type: schematic:Flip-Flop
lowx: 112000 highx: 136000 lowy: -236000 highy: -196000
rotation: 0 transpose: 0
userbits: 3072
variables: 1
SCHEM_flipflop_type[04,00/00]: "rsms"
*port: i1
arc: 70
*port: i2
arc: 2
*port: q
arc: 68
**node: 40
type: schematic:Wire_Pin
lowx: -33000 highx: -31000 lowy: -241000 highy: -239000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 58
arc: 59
**node: 41
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 2
arc: 63
**node: 42
type: schematic:Wire_Pin
lowx: 11000 highx: 13000 lowy: -233000 highy: -231000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 13
arc: 60
**node: 43
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 7168
*port: wire
arc: 35
arc: 61
arc: 62
**node: 44
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 50
arc: 64
arc: 65
**node: 45
type: schematic:Buffer
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rotation: 0 transpose: 0
userbits: 3072
*port: a
arc: 69
*port: y
arc: 70
**node: 46
type: schematic:And
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rotation: 0 transpose: 0
userbits: 3072
*port: a
arc: 66
arc: 71
arc: 73
*port: y
arc: 10
**node: 47
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 41
arc: 66
arc: 67
**node: 48
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 11
arc: 63
arc: 69
**node: 49
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 72
exported: 7
**node: 50
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 56
arc: 68
arc: 72
**node: 51
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 71
exported: 3
**node: 52
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
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arc: 73
arc: 74
**node: 53
type: schematic:And
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rotation: 0 transpose: 0
userbits: 3072
*port: a
arc: 75
arc: 78
*port: y
arc: 77
**node: 54
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 52
arc: 75
arc: 76
**node: 55
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 12
arc: 77
**node: 56
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 78
arc: 79
**node: 57
type: schematic:Wire_Pin
lowx: -33000 highx: -31000 lowy: -157000 highy: -155000
rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 79
arc: 81
arc: 82
**node: 58
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 80
arc: 81
**node: 59
type: schematic:And
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rotation: 0 transpose: 0
userbits: 7168
*port: a
arc: 83
arc: 86
arc: 89
*port: y
arc: 85
**node: 60
type: schematic:Flip-Flop
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rotation: 0 transpose: 0
userbits: 3072
variables: 1
SCHEM_flipflop_type[04,00/00]: "rsms"
*port: i1
arc: 94
*port: i2
arc: 1
*port: q
arc: 93
**node: 61
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 82
arc: 83
**node: 62
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 85
arc: 88
**node: 63
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 7168
*port: wire
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arc: 86
arc: 87
**node: 64
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 1
arc: 84
**node: 65
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
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arc: 89
arc: 90
**node: 66
type: schematic:And
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rotation: 0 transpose: 0
userbits: 3072
*port: a
arc: 91
arc: 97
arc: 100
*port: y
arc: 17
**node: 67
type: schematic:Or
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rotation: 0 transpose: 0
userbits: 3072
*port: a
arc: 14
arc: 15
arc: 17
*port: y
arc: 96
**node: 68
type: schematic:Buffer
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rotation: 0 transpose: 0
userbits: 3072
*port: a
arc: 95
*port: y
arc: 94
**node: 69
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 14
arc: 88
**node: 70
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
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arc: 91
arc: 92
**node: 71
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
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arc: 95
arc: 96
**node: 72
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 98
exported: 6
**node: 73
type: schematic:Wire_Pin
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userbits: 3072
*port: wire
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arc: 93
arc: 98
**node: 74
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 97
exported: 2
**node: 75
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 90
arc: 100
arc: 101
**node: 76
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 16
arc: 99
**node: 77
type: schematic:And
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rotation: 0 transpose: 0
userbits: 3072
*port: a
arc: 102
arc: 105
*port: y
arc: 104
**node: 78
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 76
arc: 102
arc: 103
**node: 79
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 99
arc: 104
**node: 80
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 105
arc: 106
**node: 81
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 106
arc: 108
arc: 109
**node: 82
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 107
arc: 108
**node: 83
type: schematic:Buffer
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rotation: 0 transpose: 0
userbits: 7168
*port: a
arc: 113
*port: y
arc: 112
**node: 84
type: schematic:Buffer
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rotation: 0 transpose: 0
userbits: 7168
*port: a
arc: 110
*port: y
arc: 111
**node: 85
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 110
exported: 9
**node: 86
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 7168
*port: wire
arc: 111
arc: 113
arc: 114
**node: 87
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 92
arc: 112
arc: 115
**node: 88
type: schematic:And
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rotation: 0 transpose: 0
userbits: 7168
*port: a
arc: 116
arc: 117
arc: 122
*port: y
arc: 119
**node: 89
type: schematic:Flip-Flop
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rotation: 0 transpose: 0
userbits: 68608
variables: 1
SCHEM_flipflop_type[04,00/00]: "rsms"
*port: i1
arc: 128
*port: i2
arc: 0
*port: q
arc: 125
**node: 90
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 109
arc: 116
**node: 91
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 68608
*port: wire
arc: 0
arc: 121
**node: 92
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 7168
*port: wire
arc: 114
arc: 118
**node: 93
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 7168
*port: wire
arc: 87
arc: 117
arc: 118
**node: 94
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
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arc: 120
**node: 95
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
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arc: 122
arc: 123
**node: 96
type: schematic:Buffer
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rotation: 0 transpose: 0
userbits: 68608
*port: a
arc: 127
*port: y
arc: 128
**node: 97
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rotation: 0 transpose: 0
userbits: 3072
*port: a
arc: 124
arc: 129
arc: 132
*port: y
arc: 20
**node: 98
type: schematic:Or
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rotation: 0 transpose: 0
userbits: 68608
*port: a
arc: 18
arc: 19
arc: 20
*port: y
arc: 126
**node: 99
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 19
arc: 120
**node: 100
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 115
arc: 124
**node: 101
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 68608
*port: wire
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arc: 126
arc: 127
**node: 102
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
arc: 130
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**node: 103
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
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arc: 125
arc: 130
**node: 104
type: schematic:Wire_Pin
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userbits: 3072
*port: wire
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**node: 105
type: schematic:Wire_Pin
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userbits: 3072
*port: wire
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arc: 132
**node: 106
type: schematic:Wire_Pin
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userbits: 3072
*port: wire
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arc: 131
**node: 107
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rotation: 0 transpose: 0
userbits: 3072
*port: a
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arc: 135
*port: y
arc: 134
**node: 108
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
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arc: 133
**node: 109
type: schematic:Wire_Pin
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
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arc: 134
**node: 110
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rotation: 0 transpose: 0
userbits: 3072
*port: wire
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**porttype: 0
subnode: 110
subport: wire
name: serial
descript: 3/768
userbits: -2130614272
**porttype: 1
subnode: 104
subport: wire
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userbits: -2130614272
**porttype: 2
subnode: 74
subport: wire
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userbits: -2130614272
**porttype: 3
subnode: 51
subport: wire
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userbits: -2130614272
**porttype: 4
subnode: 29
subport: wire
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userbits: -2130614272
**porttype: 5
subnode: 102
subport: wire
name: QA
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userbits: -1878956032
**porttype: 6
subnode: 72
subport: wire
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userbits: -1878956032
**porttype: 7
subnode: 49
subport: wire
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userbits: -1878956032
**porttype: 8
subnode: 27
subport: wire
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userbits: -1878956032
**porttype: 9
subnode: 85
subport: wire
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nodeport: wire
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*end: 1
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userbits: 813694978
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userbits: 813694978
*end: 0
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nodeport: wire
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*end: 1
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userbits: 813694978
*end: 0
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*end: 1
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userbits: 813694978
*end: 0
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*end: 1
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**arc: 6
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userbits: 813694978
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nodeport: wire
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*end: 1
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FACET_message[0257204,00/00]: ["-- VHDL design of Automobile Cruise Control","-- for 1988 CMC Workshop","--","-- Written by: D. Luke, A. Jost, & R. Hobson","-- Revised to IEEE syntax by A. Jost","-- Latest revision date: Jan 3, 1989","-- *********************************************","","--BUS STRUCTURE DEFINITION","","package buses is","        type BUS8 is array (0 to 7) of BIT;","end buses;","","--**********************","","--TOP LEVEL ENTITY ACC","","use buses.all;","","entity ACC is port(DR_SPEED, CONTROL : in BIT; FASTER, SLOWER : out BIT;","                REF_SPEED: in BUS8)  ;","end ACC;","","-- how it is constructed:","","architecture ACC_BODY of ACC is","","    component   SENSOR_BOX port(pulses,reset : in BIT; refer: in BUS8;","                        equal : out BIT);","    end component;","","    component   TRANSMITTER_BOX1 port( eq, ck: in BIT;","                        su, sd: out BIT);","    end component;","","    signal      EQUAL: BIT;","","begin","","SENSOR:         SENSOR_BOX port map( DR_SPEED, CONTROL, REF_SPEED, EQUAL);","TRANSMITTER:    TRANSMITTER_BOX1 port map( EQUAL, CONTROL, FASTER, SLOWER);","","end ACC_BODY;","","--*******************************************************","","--ENTITY SENSOR_BOX","","use buses.all;","","entity SENSOR_BOX is port(pulses, reset: in BIT; refer: in BUS8;","                          equal: out BIT) ;","end SENSOR_BOX;","","architecture SENSOR_BODY of SENSOR_BOX is","     ","        component COUNTER_8 port(pulses,reset: in BIT; c: out BUS8);","	end component;","","        component COMPARATOR_8 port(ina,inb: in BUS8;eql: out BIT);","	end component;","","        signal C: BUS8;","","begin","","COUNTER:        COUNTER_8 port map(pulses,reset,C);","COMPARATOR:     COMPARATOR_8 port map(C,refer,equal);","","end SENSOR_BODY;","","--***********************************************","","-- ENTITY TRANSMITTER_BOX","","entity TRANSMITTER_BOX1 is port( eq, ck: in BIT; su, sd: out BIT) ;","end TRANSMITTER_BOX1;","","architecture TRANSMITTER_BODY1 of TRANSMITTER_BOX1 is","","        component rdff port(d,ck,cb,reset: in BIT; q,qb: out BIT);","	end component;","","        component inverter port(a: in BIT; y: out BIT);","	end component;","","        component nor2 port(a1,a2: in BIT; y: out BIT);","	end component;","","        component nor3 port(a1,a2,a3: in BIT; y: out BIT);","	end component;","","        signal ckbar,q1b,power,q2,q2b: BIT;","","begin","","FF1:    rdff port map(power,ck,ckbar,eq,open,q1b);","FF21:   nor2 port map(eq,q2b,q2);","FF22:   nor2 port map(q2,ck,q2b);","NOR3X:  nor3 port map(q2b,ck,su,sd);","INV:    inverter port map(ck,ckbar);","NORX:   nor2 port map(ck,q1b,su);","","end TRANSMITTER_BODY1;","","--********************************************","","--ENTITY COUNTER_8","","use buses.all;","","entity COUNTER_8 is port(pulses, reset: in BIT; c:out BUS8);","end COUNTER_8;","","architecture COUNTER_BODY of COUNTER_8 is","","    component    rdff port(d, ck, cb, reset : in BIT; q, qb: out BIT);","    end component;","","    component    inverter port(a: in BIT; y: out BIT);","    end component;","","    signal       CBAR: BUS8;","    signal       DSBAR: BIT;","    signal       HOLD: BIT;","","begin","","RIPPLEADD:  for i in 1 to 7 generate","    RIPPLE:  rdff port map(CBAR(i), CBAR(i-1), C(i-1), HOLD, C(i), CBAR(i));","            end generate RIPPLEADD;","","RIPPLEIN:   rdff port map(CBAR(0), pulses, DSBAR, HOLD, C(0), CBAR(0));","DS_INVERT:  inverter port map(pulses, DSBAR);","R_INVERT:   inverter port map(RESET, HOLD);","","end COUNTER_BODY;","","--*************************************************","","-- ENTITY COMPARATOR_8","","use buses.all;","","entity COMPARATOR_8 is port(ina, inb:in BUS8; eql: out BIT);","end COMPARATOR_8;","","architecture COMPARATOR_BODY of COMPARATOR_8 is","","        component xor2 port(a1,a2: in BIT; y,yb: out BIT);","	end component;","","        component nor2 port(a1,a2: in BIT; y: out BIT);","	end component;","","        component nand4 port(a1,a2,a3,a4: in BIT; y : out BIT);","	end component;","","        signal comp: BUS8;","        signal p,q: BIT;","","begin","","XORG:   for i in 0 to 7 generate","           XORX: xor2 port map(ina(i),inb(i),open,comp(i));","        end generate XORG;","NANDX1: nand4 port map(comp(0),comp(1),comp(2),comp(3),p);","NANDX2: nand4 port map(comp(4),comp(5),comp(6),comp(7),q);","NORX:   nor2 port map(p,q,eql);","","end COMPARATOR_BODY;","","--***************************************************************",""]
celldone: tool-SiliconCompiler
***cell: 21
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celldone: tool-SimulateALS
***cell: 22
name: DCVoltage{ic}
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creationdate: 1006816118
revisiondate: 1006988902
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externallibrary: "C:\DevelE\Electric\lib\spiceparts.txt"
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name: Pulse{ic}
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NODE_name[04,00/0400]: "pmos1"
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celldone: tool-SimulateSPICE
***cell: 25
name: tool-SimulateVERILOG{sch}
version: 1
creationdate: 923075962
revisiondate: 1012002997
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NODE_name[04,00/00]: "node5"
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NODE_name[04,00/00]: "node3"
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VERILOG_declaration[02304,04/0400]: ["wire b, c;","wire e, f;"]
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VERILOG_code[02304,04/0400]: ["a = b + c;","b = e - f;"]
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arc: 18
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arc: 21
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subport: bus
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ARC_name[0104,010020001/0400]: "z^[3^]"
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nodeport: a
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ARC_name[0104,010140001/0400]: "z^[2^]"
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ARC_name[04,00/00]: "net1"
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ARC_name[0104,01/0400]: "z^[1^]"
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ARC_name[0104,00/0400]: "d^[0^]"
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ARC_name[0104,00/0400]: "d^[1^]"
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ARC_name[0104,00/0400]: "d^[2^]"
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ARC_name[0104,00/0400]: "d^[3^]"
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ARC_name[0104,0100000000/0400]: "d^[0:3^]"
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nodeport: y
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celldone: tool-SimulateVERILOG
***cell: 26
name: tech-RoundCMOS{lay}
version: 1
creationdate: 902347845
revisiondate: 902350978
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celldone: tech-RoundCMOS
***cell: 27
name: tool-PadFrame{lay}
version: 1
creationdate: 979330051
revisiondate: 985890961
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nodeport: wire
xpos: 100000 ypos: -48000
*end: 1
node: 21
nodeport: gnd
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**arc: 33
type: schematic:wire
width: 0 length: 12000
userbits: 1904222658
*end: 0
node: 30
nodeport: wire
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*end: 1
node: 24
nodeport: s
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celldone: tool_NCC
