Using Electric 9-3: Electrical-Rule Checking

Chapter 9: TOOLS

| ## 9-3: Electrical-Rule Checking |

The electrical-rule checker (ERC) is a collection of tools for checking a circuit's behavior without simulation. Currently, the only check that is done is the Well areas of a CMOS chip.

To run the ERC, use the Analyze Wells subcommand of the Electrical Rules command of the Tools menu. This may take some time, and if it takes too long, you can abort it with the interrupt key (see Section 1-9).

After analysis is done, you can review the errors by typing:

- ">" to see the next error
- "<" to see the previous error

The Electrical Rules Checker makes sure that there are well contacts in every area of well. You can relax this restriction with the ERC Options... command. This dialog allows you to request that there be only 1 well contact, anywhere on the chip. You can also instruct the ERC to ignore contacts entirely. |

The ERC also checks spacing rules between well areas. Although this is generally the domain of the Design Rule Checker, it is not done there, so it is done here.

The ERC also checks that there is a connection to power and ground in the appropriate places. You can disable these checks in the ERC Options... dialog.

Finally, the ERC reports the maximum distance from a well contact to any point on the well. This is useful when making sure that there are sufficient contacts for each area.

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