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\subsection{ARM32 Calling Conventions}

\paragraph{Overview}

The ARM32 family of processors is based on the Advanced RISC Machines (ARM)
processor architecture (32 bit RISC).
The word size is 32 bits (and the programming model is LLP64).\\
Basically, this family of microprocessors can be run in 2 major modes:\\
\\
\begin{tabular*}{0.95\textwidth}{2 B}
Mode          & Description\\
\hline
{\bf ARM}     & 32bit instruction set\\
{\bf THUMB}   & compressed instruction set using 16bit wide instruction encoding\\
\end{tabular*}
\\
\\
For more details, take a look at the ARM-THUMB Procedure Call Standard (ATPCS)
\cite{ATPCS}, the Procedure Call Standard for the ARM Architecture (AAPCS)
\cite{AAPCS}, as well as Debian's ARM EABI port \cite{armeabi} and hard-float
\cite{armhf} wiki pages.\\ \\

\paragraph{\product{dyncall} support}

Currently, the \product{dyncall} library supports the ARM and THUMB mode of the
ARM32 family (ATPCS \cite{ATPCS}, EABI \cite{armeabi}, the ARM hard-float
(armhf) \cite{armeabi} varian, as well as Apple's calling convention based on
the ATPCS), excluding manually triggered ARM-THUMB interworking calls.\\
Also supported is armhf, a calling convention with register support to pass
floating point numbers. FPA and the VFP (scalar mode) procedure call standards,
as well as some instruction sets accelerating DSP and multimedia application
like the ARM Jazelle Technology (direct Java bytecode execution, providing
acceleration for some bytecodes while calling software code for others), etc.,
are not supported by the dyncall library.\\


\subsubsection{ATPCS ARM mode}


\paragraph{Registers and register usage}

In ARM mode, the ARM32 processor has sixteen 32 bit general purpose registers, namely r0-r15:\\
\\
\begin{table}[h]
\begin{tabular*}{0.95\textwidth}{lll}
Name        & Alias       & Brief description\\
\hline
{\bf r0}    & {\bf a1}    & parameter 0, scratch, return value\\
{\bf r1}    & {\bf a2}    & parameter 1, scratch, return value\\
{\bf r2,r3} & {\bf a3,a4} & parameters 2 and 3, scratch\\
{\bf r4-r9} & {\bf v1-v6} & permanent\\
{\bf r10}   & {\bf sl}    & permanent\\
{\bf r11}   & {\bf fp}    & frame pointer, permanent\\
{\bf r12}   & {\bf ip}    & scratch\\
{\bf r13}   & {\bf sp}    & stack pointer, permanent\\
{\bf r14}   & {\bf lr}    & link register, permanent\\
{\bf r15}   & {\bf pc}    & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\
\end{tabular*}
\caption{Register usage on arm32}
\end{table}

\paragraph{Parameter passing}

\begin{itemize}
\item stack parameter order: right-to-left
\item caller cleans up the stack
\item first four words are passed using r0-r3
\item subsequent parameters are pushed onto the stack (in right to left order, such that the stack pointer points to the first of the remaining parameters)
\item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first four words to a reserved stack area adjacent to the other parameters on the stack
\item parameters \textless=\ 32 bits are passed as 32 bit words
\item 64 bit parameters are passed as two 32 bit parts (even partly via the register and partly via the stack, although this doesn't seem to be specified in the ATPCS)
\item aggregates (struct, union) are passed by value (after rounding up the size to the nearest multiple of 4), as a sequence of words (splitting across registers and stack is allowed)
\item {\it non-trivial} C++ aggregates (as defined by the language) of any size, are passed indirectly via a pointer to a copy of the aggregate
\item keeping the stack eight-byte aligned can improve memory access performance and is required by LDRD and STRD on ARMv5TE processors which are part of the ARM32 family, so, in order to avoid problems one should always align the stack (tests have shown, that GCC does care about the alignment when using the ellipsis)
\end{itemize}

\paragraph{Return values}

\begin{itemize}
\item return values \textless=\ 32 bits use r0
\item 64 bit return values use r0 and r1
\item for {\it non-trivial} C++ aggregates, the caller allocates space, passes pointer to it to the callee as a hidden first param
(meaning in r0), and callee writes return value to this space; the ptr to the aggregate is returned in r0
\item aggregates (struct, union) \textless=\ 32 bits are returned like an integer (in r0)
\item aggregates (struct, union) \textgreater\ 32 bits the caller allocates space for the return value on the stack in its frame and passes a pointer to it in r0
\item for all other aggregates, the caller allocates space, passes pointer to it to the callee as a hidden first param (meaning in r0), and callee writes return value to this space; the ptr to the aggregate is returned in r0
\end{itemize}

\paragraph{Stack layout}

% verified/amended: TP nov 2019 (see also doc/disas_examples/arm.atpcs_arm.disas)
Stack directly after function prolog:\\

\begin{figure}[h]
\begin{tabular}{5|3|1 1}
                                         & \vdots               &                                      &                              \\
\hhline{~=~~}
register save area                       & \hspace{4cm}         &                                      & \mrrbrace{5}{caller's frame} \\
\hhline{~-~~}
local data                               &                      &                                      &                              \\
\hhline{~-~~}
\mrlbrace{7}{parameter area}             & last arg             & \mrrbrace{3}{stack parameters}       &                              \\
                                         & \ldots               &                                      &                              \\
                                         & 5th word of arg data &                                      &                              \\
\hhline{~=~~}
                                         & r3                   & \mrrbrace{4}{spill area (if needed)} & \mrrbrace{7}{current frame}  \\
                                         & r2                   &                                      &                              \\
                                         & r1                   &                                      &                              \\
                                         & r0                   &                                      &                              \\
\hhline{~-~~}
register save area (with return address) &                      &                                      &                              \\ %fp points here to 1st word of this area: $\leftarrow$ fp
\hhline{~-~~}
local data                               &                      &                                      &                              \\
\hhline{~-~~}
parameter area                           & \vdots               &                                      &                              \\
\end{tabular}
\caption{Stack layout on arm32}
\end{figure}


\clearpage


\subsubsection{ATPCS THUMB mode}


\paragraph{Status}

\paragraph{Registers and register usage}

In THUMB mode, the ARM32 processor family supports eight 32 bit general purpose registers r0-r7 and access to high order registers r8-r15:\\
\\
\begin{table}[h]
\begin{tabular*}{0.95\textwidth}{lll}
Name         & Alias       & Brief description\\
\hline
{\bf r0}     & {\bf a1}    & parameter 0, scratch, return value\\
{\bf r1}     & {\bf a2}    & parameter 1, scratch, return value\\
{\bf r2,r3}  & {\bf a3,a4} & parameters 2 and 3, scratch\\
{\bf r4-r6}  & {\bf v1-v3} & permanent\\
{\bf r7}     & {\bf v4}    & frame pointer, permanent\\
{\bf r8-r11} & {\bf v5-v8} & permanent\\
{\bf r12}    & {\bf ip}    & scratch\\
{\bf r13}    & {\bf sp}    & stack pointer, permanent\\
{\bf r14}    & {\bf lr}    & link register, permanent\\
{\bf r15}    & {\bf pc}    & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\
\end{tabular*}
\caption{Register usage on arm32 thumb mode}
\end{table}

\paragraph{Parameter passing}

\begin{itemize}
\item stack parameter order: right-to-left
\item caller cleans up the stack
\item first four words are passed using r0-r3
\item subsequent parameters are pushed onto the stack (in right to left order, such that the stack pointer points to the first of the remaining parameters)
\item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first four words to a reserved stack area adjacent to the other parameters on the stack
\item parameters \textless=\ 32 bits are passed as 32 bit words
\item 64 bit parameters are passed as two 32 bit parts (even partly via the register and partly via the stack, although this doesn't seem to be specified in the ATPCS)
\item aggregates (struct, union) are passed by value (after rounding up the size to the nearest multiple of 4), as a sequence of words (splitting across registers and stack is allowed)
\item {\it non-trivial} C++ aggregates (as defined by the language) of any size, are passed indirectly via a pointer to a copy of the aggregate
\item keeping the stack eight-byte aligned can improve memory access performance and is required by LDRD and STRD on ARMv5TE processors which are part of the ARM32 family, so, in order to avoid problems one should always align the stack (tests have shown, that GCC does care about the alignment when using the ellipsis)
\end{itemize}

\paragraph{Return values}

\begin{itemize}
\item return values \textless=\ 32 bits use r0
\item 64 bit return values use r0 and r1
\item for {\it non-trivial} C++ aggregates, the caller allocates space, passes pointer to it to the callee as a hidden first param
(meaning in r0), and callee writes return value to this space; the ptr to the aggregate is returned in r0
\item aggregates (struct, union) \textless=\ 32 bits are returned like an integer (in r0)
\item aggregates (struct, union) \textgreater\ 32 bits the caller allocates space for the return value on the stack in its frame and passes a pointer to it in r0
\item for all other aggregates, the caller allocates space, passes pointer to it to the callee as a hidden first param (meaning in r0), and callee writes return value to this space; the ptr to the aggregate is returned in r0
\end{itemize}

\paragraph{Stack layout}

Stack directly after function prolog:\\

\begin{figure}[h]
\begin{tabular}{5|3|1 1}
                                         & \vdots               &                                      &                              \\
\hhline{~=~~}                                                  
register save area                       & \hspace{4cm}         &                                      & \mrrbrace{5}{caller's frame} \\
\hhline{~-~~}                                                  
local data                               &                      &                                      &                              \\
\hhline{~-~~}                                                  
\mrlbrace{7}{parameter area}             & last arg             & \mrrbrace{3}{stack parameters}       &                              \\
                                         & \ldots               &                                      &                              \\
                                         & 5th word of arg data &                                      &                              \\
\hhline{~=~~}                                                  
                                         & r3                   & \mrrbrace{4}{spill area (if needed)} & \mrrbrace{7}{current frame}  \\
                                         & r2                   &                                      &                              \\
                                         & r1                   &                                      &                              \\
                                         & r0                   &                                      &                              \\
\hhline{~-~~}                                                  
register save area (with return address) &                      &                                      &                              \\ %fp points here to 1st word of this area: $\leftarrow$ fp
\hhline{~-~~}                                                  
local data                               &                      &                                      &                              \\
\hhline{~-~~}                                                  
parameter area                           & \vdots               &                                      &                              \\
\end{tabular}
\caption{Stack layout on arm32 thumb mode}
\end{figure}


\clearpage


\subsubsection{EABI (ARM and THUMB mode)}


The ARM EABI is very similar to the ABI outlined in ARM-THUMB procedure call
standard (ATPCS) \cite{ATPCS} - however, the EABI requires the stack to be
8-byte aligned at function entries, as well as for 64 bit parameters. The latter
are aligned on 8-byte boundaries on the stack and 2-registers for a parameter
passed via register. In order to achieve such an alignment, a register might
have to be skipped for parameters passed via registers, or 4-bytes on the stack
for parameters passed via the stack. Refer to the Debian ARM EABI port wiki
for more information \cite{armeabi}.\\


\clearpage


\subsubsection{ARM on Apple's iOS (Darwin) Platform (ARM and THUMB mode)}


The iOS runs on ARMv6 (iOS 2.0) and ARMv7 (iOS 3.0) architectures. Both, ARM and THUMB are available,
code is usually compiled in THUMB mode.\\
\\
\paragraph{Register usage}

\begin{table}[h]
\begin{tabular*}{0.95\textwidth}{lll}
Name         & Alias    & Brief description\\
\hline
{\bf r0}     &          & parameter 0, scratch, return value\\
{\bf r1}     &          & parameter 1, scratch, return value\\
{\bf r2,r3}  &          & parameters 2 and 3, scratch\\
{\bf r4-r6}  &          & permanent\\
{\bf r7}     &          & frame pointer, permanent\\
{\bf r8}     &          & permanent\\
{\bf r9}     &          & permanent (iOS 2.0) / scratch (since iOS 3.0)\\
{\bf r10-r11}&          & permanent\\
{\bf r12}    &          & scratch, intra-procedure scratch register (IP) used by dynamic linker\\
{\bf r13}    & {\bf sp} & stack pointer, permanent\\
{\bf r14}    & {\bf lr} & link register, permanent\\
{\bf r15}    & {\bf pc} & program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\
{\bf cpsr}   &          & program status register\\
{\bf d0-d7}  &          & scratch, aliases s0-s15, on ARMv7 also as q0-q3; not accessible from Thumb mode on ARMv6\\
{\bf d8-d15} &          & permanent, aliases s16-s31, on ARMv7 also as q4-q7; not accesible from Thumb mode on ARMv6\\
{\bf d16-d31}&          & only available in ARMv7, aliases q8-q15\\
{\bf fpscr}  &          & VFP status register\\
\end{tabular*}
\caption{Register usage on ARM Apple iOS}
\end{table}

\paragraph{Parameter passing and Return values}

The ABI is based on the AAPCS but with the following important differences:

\begin{itemize}
\item in ARM mode, r7 is used as frame pointer instead of r11 (so both, ARM and THUMB mode use the same convention)
\item r9 does not need to be preserved on iOS 3.0 and greater
\end{itemize}


\clearpage

\paragraph{Stack layout}

% verified/amended: TP nov 2019 (see also doc/disas_examples/arm.darwin_{arm,thumb}.disas)
Stack directly after function prolog:\\

\begin{figure}[h]
\begin{tabular}{5|3|1 1}
                                         & \vdots               &                                      &                              \\
\hhline{~=~~}                                                  
register save area                       & \hspace{4cm}         &                                      & \mrrbrace{5}{caller's frame} \\
\hhline{~-~~}                                                  
local data                               &                      &                                      &                              \\
\hhline{~-~~}                                                  
\mrlbrace{7}{parameter area}             & last arg             & \mrrbrace{3}{stack parameters}       &                              \\
                                         & \ldots               &                                      &                              \\
                                         & 5th word of arg data @@@verify &                                      &                              \\
\hhline{~=~~}                                                  
                                         & r3                   & \mrrbrace{4}{spill area (if needed)} & \mrrbrace{7}{current frame}  \\
                                         & r2                   &                                      &                              \\
                                         & r1                   &                                      &                              \\
                                         & r0                   &                                      &                              \\
\hhline{~-~~}                                                  
register save area (with return address) &                      &                                      &                              \\ %fp points here to 1st word of this area: $\leftarrow$ fp
\hhline{~-~~}                                                  
local data                               &                      &                                      &                              \\
\hhline{~-~~}                                                  
parameter area                           & \vdots               &                                      &                              \\
\end{tabular}
\caption{Stack layout on arm32 (Apple)}
\end{figure}


\clearpage


\subsubsection{ARM hard float (armhf)}


Most debian-based Linux systems on ARMv7 (or ARMv6 with FPU) platforms use a calling convention referred to
as armhf, using 16 32-bit floating point registers of the FPU of the VFPv3-D16 extension to the ARM architecture.
Refer to the debian wiki for more information \cite{armhf}. % The following is for ARM mode, find platform that uses thumb+hard-float @@@

Code is little-endian, rest is similar to EABI with an 8-byte aligned stack, etc..\\
\\
\paragraph{Register usage}

\begin{table}[h]
\begin{tabular*}{0.95\textwidth}{lll}
Name         & Alias       &  Brief description\\
\hline          
{\bf r0}     & {\bf a1}    &  parameter 0, scratch, non floating point return value\\
{\bf r1}     & {\bf a2}    &  parameter 1, scratch, non floating point return value\\
{\bf r2,r3}  & {\bf a3,a4} &  parameters 2 and 3, scratch\\
{\bf r4-r9}  & {\bf v1-v6} &  permanent\\
{\bf r10}    & {\bf sl}    &  permanent\\
{\bf r11}    & {\bf fp}    &  frame pointer, permanent\\
{\bf r12}    & {\bf ip}    &  scratch, intra-procedure scratch register (IP) used by dynamic linker\\
{\bf r13}    & {\bf sp}    &  stack pointer, permanent\\
{\bf r14}    & {\bf lr}    &  link register, permanent\\
{\bf r15}    & {\bf pc}    &  program counter (note: due to pipeline, r15 points to 2 instructions ahead)\\
{\bf cpsr}   &             &  program status register\\
{\bf s0}     &             &  floating point argument, floating point return value, single precision\\
{\bf d0}     &             &  floating point argument, floating point return value, double precision, aliases s0-s1\\
{\bf s1-s15} &             &  floating point arguments, single precision\\
{\bf d1-d7}  &             &  aliases s2-s15, floating point arguments, double precision\\
{\bf fpscr}  &             &  VFP status register\\
\end{tabular*}
\caption{Register usage on armhf}
\end{table}

\paragraph{Parameter passing}

\begin{itemize}
\item stack parameter order: right-to-left
\item caller cleans up the stack
\item first four non-floating-point words are passed using r0-r3
\item out of those, 64bit parameters use 2 registers, either r0,r1 or r2,r3 (skipped registers are left unused)
\item first 16 single-precision, or 8 double-precision arguments are passed via s0-s15 or d0-d7, respectively (note that since s and d registers are aliased, already used ones are skipped)
\item subsequent parameters are pushed onto the stack (in right to left order, such that the stack pointer points to the first of the remaining parameters)
\item note that as soon one floating point parameter is passed via the stack, subsequent single precision floating point parameters are also pushed onto the stack even if there are still free S* registers
\item float and double vararg function parameters (no matter if in ellipsis part of function, or not) are passed like int or long long parameters, vfp registers aren't used
\item if the callee takes the address of one of the parameters and uses it to address other parameters (e.g. varargs) it has to copy - in its prolog - the first four words (for first 4 integer arguments) to a reserved stack area adjacent to the other parameters on the stack
\item parameters \textless=\ 32 bits are passed as 32 bit words
\item aggregates (struct, union) with 1 to 4 identical floating-point members (either float or double) are passed field-by-field, except if passed as a vararg
\item aggregates that could be passed via floating point register are never split across those and the stack, so if not enough registers are available an aggregate is
passed entirely via the stack (implying above rule that any still unused float registers will be skipped for any subsequent arg)
\item {\it non-trivial} C++ aggregates (as defined by the language) of any size, are passed indirectly via a pointer to a copy of the aggregate
\item all other aggregates (struct, union), after rounding up the size to the nearest multiple of 4, are passed as a sequence of dwords, like integers (splitting across registers and stack is allowed)
\item callee spills, caller reserves spill area space, though
\end{itemize}

\paragraph{Return values}

\begin{itemize}
\item non floating point return values \textless=\ 32 bits use r0
\item non floating point 64-bit return values use r0 and r1
\item floating point return value uses s0 (for float) or d0 (for double), respectively
\item for {\it non-trivial} C++ aggregates, the caller allocates space, passes pointer to it to the callee as a hidden first param
(meaning in r0), and callee writes return value to this space; the ptr to the aggregate is returned in r0
\item aggregates (struct, union) with 1 to 4 identical floating-point members are returned in s0-s3 (for float) or d0-d3 (for double), respectively
\item all other aggregates \textless=\ 32 bits are returned via r0
\item for all other aggregates, the caller allocates space, passes pointer to it to the callee as a hidden first param
(meaning in r0), and callee writes return value to this space; the ptr to the aggregate is returned in r0
\end{itemize}

\paragraph{Stack layout}

% verified/amended: TP nov 2019 (see also doc/disas_examples/arm.armhf.disas)
Stack directly after function prolog:\\

\begin{figure}[h]
\begin{tabular}{5|3|1 1}
                                         & \vdots                     &                                      &                              \\
\hhline{~=~~}
register save area                       & \hspace{4cm}               &                                      & \mrrbrace{5}{caller's frame} \\
\hhline{~-~~}
local data                               &                            &                                      &                              \\
\hhline{~-~~}
\mrlbrace{7}{parameter area}             & last arg                   & \mrrbrace{3}{stack parameters}       &                              \\
                                         & \ldots                     &                                      &                              \\
                                         & first arg passed via stack &                                      &                              \\
\hhline{~=~~}
                                         & r3                         & \mrrbrace{4}{spill area (if needed)} & \mrrbrace{7}{current frame}  \\
                                         & r2                         &                                      &                              \\
                                         & r1                         &                                      &                              \\
                                         & r0                         &                                      &                              \\
\hhline{~-~~}
register save area (with return address) &                            &                                      &                              \\ %fp points here to 1st word of this area: $\leftarrow$ fp
\hhline{~-~~}
local data                               &                            &                                      &                              \\
\hhline{~-~~}
parameter area                           & \vdots                     &                                      &                              \\
\end{tabular}
\caption{Stack layout on arm32 armhf}
\end{figure}


\clearpage


\subsubsection{Architectures}

The ARM architecture family contains several revisions with capabilities and
extensions (such as thumb-interworking, more vector registers, ...)
The following table sums up the most important properties of the various
architecture standards, from a calling convention perspective.

% iPhone 3GS : ARM Cortex-A8
% Nintendo DS: ARM 7 and ARM 9
% ARM 7: ARMv4T
% ARM 9: ARMv4T, HTC Wizard
% Cortex-*: ARMv7, Raspberry Pi 2, ...

\begin{table}[h]
\begin{tabular*}{0.95\textwidth}{lll}
Arch   & Platforms & Details \\
\hline
ARMv4  &                                          & \\
ARMv4T & ARM 7, ARM 9, Neo FreeRunner (OpenMoko)  & \\
ARMv5  & ARM 9E                                   & BLX instruction available \\
ARMv6  &                                          & No vector registers available in thumb \\
ARMv7  & iPod touch, iPhone 3GS/4, Raspberry Pi 2 & VFP, armhf convention on some platforms \\
ARMv8  & iPhone 6 and higher                      & 64bit support \\
\end{tabular*}
\caption{Overview of ARM Architecture, Platforms and Details}
\end{table}

