patch-2.4.1 linux/arch/ppc/kernel/open_pic.c
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- Lines: 955
- Date:
Mon Jan 22 15:41:15 2001
- Orig file:
v2.4.0/linux/arch/ppc/kernel/open_pic.c
- Orig date:
Sun Sep 17 09:48:07 2000
diff -u --recursive --new-file v2.4.0/linux/arch/ppc/kernel/open_pic.c linux/arch/ppc/kernel/open_pic.c
@@ -1,5 +1,5 @@
/*
- * arch/ppc/kernel/openpic.c -- OpenPIC Interrupt Handling
+ * arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
*
* Copyright (C) 1997 Geert Uytterhoeven
*
@@ -13,35 +13,38 @@
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
-#include <linux/openpic.h>
+#include <linux/irq.h>
#include <asm/ptrace.h>
#include <asm/signal.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/prom.h>
+
#include "local_irq.h"
+#include "open_pic.h"
+#include "open_pic_defs.h"
-volatile struct OpenPIC *OpenPIC = NULL;
+void* OpenPIC_Addr;
+static volatile struct OpenPIC *OpenPIC = NULL;
u_int OpenPIC_NumInitSenses __initdata = 0;
u_char *OpenPIC_InitSenses __initdata = NULL;
-int open_pic_irq_offset;
extern int use_of_interrupt_tree;
-void chrp_mask_irq(unsigned int);
-void chrp_unmask_irq(unsigned int);
void find_ISUs(void);
static u_int NumProcessors;
static u_int NumSources;
-OpenPIC_Source *ISU;
-/*
- * We should use this if we have > 1 ISU.
- * We can just point each entry to the
- * appropriate source regs but it wastes a lot of space
- * so until we have >1 ISU I'll leave it unimplemented.
- * -- Cort
-OpenPIC_Source ISU[128];
-*/
+#ifdef CONFIG_POWER3
+static int NumISUs;
+#endif
+static int open_pic_irq_offset;
+static volatile unsigned char* chrp_int_ack_special;
+
+OpenPIC_SourcePtr ISU[OPENPIC_MAX_ISU];
+
+static void openpic_end_irq(unsigned int irq_nr);
+static void openpic_ack_irq(unsigned int irq_nr);
+static void openpic_set_affinity(unsigned int irq_nr, unsigned long cpumask);
struct hw_interrupt_type open_pic = {
" OpenPIC ",
@@ -49,45 +52,69 @@
NULL,
openpic_enable_irq,
openpic_disable_irq,
- 0,
+ openpic_ack_irq,
+ openpic_end_irq,
+ openpic_set_affinity
+};
+
+#ifdef CONFIG_SMP
+static void openpic_end_ipi(unsigned int irq_nr);
+static void openpic_ack_ipi(unsigned int irq_nr);
+static void openpic_enable_ipi(unsigned int irq_nr);
+static void openpic_disable_ipi(unsigned int irq_nr);
+
+struct hw_interrupt_type open_pic_ipi = {
+ " OpenPIC ",
+ NULL,
+ NULL,
+ openpic_enable_ipi,
+ openpic_disable_ipi,
+ openpic_ack_ipi,
+ openpic_end_ipi,
0
};
+#endif /* CONFIG_SMP */
/*
- * Accesses to the current processor's registers
+ * Accesses to the current processor's openpic registers
*/
-#ifndef __powerpc__
-#define THIS_CPU Private
-#define CHECK_THIS_CPU do {} while (0)
-#else
+#ifdef CONFIG_SMP
#define THIS_CPU Processor[cpu]
+#define DECL_THIS_CPU int cpu = smp_hw_index[smp_processor_id()]
#define CHECK_THIS_CPU check_arg_cpu(cpu)
-#endif
+#else
+#define THIS_CPU Processor[0]
+#define DECL_THIS_CPU
+#define CHECK_THIS_CPU
+#endif /* CONFIG_SMP */
#if 1
#define check_arg_ipi(ipi) \
if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
- printk("openpic.c:%d: illegal ipi %d\n", __LINE__, ipi);
+ printk("open_pic.c:%d: illegal ipi %d\n", __LINE__, ipi);
#define check_arg_timer(timer) \
if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
- printk("openpic.c:%d: illegal timer %d\n", __LINE__, timer);
+ printk("open_pic.c:%d: illegal timer %d\n", __LINE__, timer);
#define check_arg_vec(vec) \
if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
- printk("openpic.c:%d: illegal vector %d\n", __LINE__, vec);
+ printk("open_pic.c:%d: illegal vector %d\n", __LINE__, vec);
#define check_arg_pri(pri) \
if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
- printk("openpic.c:%d: illegal priority %d\n", __LINE__, pri);
+ printk("open_pic.c:%d: illegal priority %d\n", __LINE__, pri);
/*
- * I changed this to return to keep us from from trying to use irq #'s
- * that we're using for IPI's.
- * -- Cort
- */
+ * Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
+ * data has probably been corrupted and we're going to panic or deadlock later
+ * anyway --Troy
+ */
+extern unsigned long* _get_SP(void);
#define check_arg_irq(irq) \
- /*if (irq < 0 || irq >= (NumSources+open_pic_irq_offset)) \
- printk("openpic.c:%d: illegal irq %d\n", __LINE__, irq);*/
+ if (irq < open_pic_irq_offset || irq >= (NumSources+open_pic_irq_offset)){ \
+ printk("open_pic.c:%d: illegal irq %d\n", __LINE__, irq); \
+ print_backtrace(_get_SP()); }
#define check_arg_cpu(cpu) \
- if (cpu < 0 || cpu >= NumProcessors) \
- printk("openpic.c:%d: illegal cpu %d\n", __LINE__, cpu);
+ if (cpu < 0 || cpu >= NumProcessors){ \
+ printk("open_pic.c:%d: illegal cpu %d\n", __LINE__, cpu); \
+ print_backtrace(_get_SP()); }
#else
#define check_arg_ipi(ipi) do {} while (0)
#define check_arg_timer(timer) do {} while (0)
@@ -97,23 +124,10 @@
#define check_arg_cpu(cpu) do {} while (0)
#endif
-#ifdef CONFIG_SMP
-void openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
-{
- smp_message_recv(cpl-OPENPIC_VEC_IPI, regs);
-}
-#endif /* CONFIG_SMP */
-
-#ifdef __i386__
-static inline u_int in_le32(volatile u_int *addr)
-{
- return *addr;
-}
-
-static inline void out_le32(volatile u_int *addr, u_int val)
-{
- *addr = val;
-}
+#ifdef CONFIG_POWER3
+ #define GET_ISU(source) ISU[(source) >> 4][(source) & 0xf]
+#else
+ #define GET_ISU(source) ISU[0][(source)]
#endif
u_int openpic_read(volatile u_int *addr)
@@ -156,22 +170,66 @@
u_int field)
{
openpic_setfield(addr, OPENPIC_MASK);
- /* wait until it's not in use */
- /* BenH: Is this code really enough ? I would rather check the result
- * and eventually retry ...
- */
while (openpic_read(addr) & OPENPIC_ACTIVITY);
openpic_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
}
-void __init openpic_init(int main_pic)
+#ifdef CONFIG_SMP
+/* yes this is right ... bug, feature, you decide! -- tgall */
+u_int openpic_read_IPI(volatile u_int* addr)
+{
+ u_int val = 0;
+#ifdef CONFIG_POWER3
+ val = in_be32(addr);
+#else
+ val = in_le32(addr);
+#endif
+ return val;
+}
+
+/* because of the power3 be / le above, this is needed */
+inline void openpic_writefield_IPI(volatile u_int* addr, u_int mask, u_int field)
+{
+ u_int val = openpic_read_IPI(addr);
+ openpic_write(addr, (val & ~mask) | (field & mask));
+}
+
+static inline void openpic_clearfield_IPI(volatile u_int *addr, u_int mask)
+{
+ openpic_writefield_IPI(addr, mask, 0);
+}
+
+static inline void openpic_setfield_IPI(volatile u_int *addr, u_int mask)
+{
+ openpic_writefield_IPI(addr, mask, mask);
+}
+
+static void openpic_safe_writefield_IPI(volatile u_int *addr, u_int mask, u_int field)
+{
+ openpic_setfield_IPI(addr, OPENPIC_MASK);
+
+ /* wait until it's not in use */
+ /* BenH: Is this code really enough ? I would rather check the result
+ * and eventually retry ...
+ */
+ while(openpic_read_IPI(addr) & OPENPIC_ACTIVITY);
+
+ openpic_writefield_IPI(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
+}
+#endif /* CONFIG_SMP */
+
+void __init openpic_init(int main_pic, int offset, unsigned char* chrp_ack,
+ int programmer_switch_irq)
{
u_int t, i;
u_int timerfreq;
const char *version;
- if (!OpenPIC)
- panic("No OpenPIC found");
+ if (!OpenPIC_Addr) {
+ printk("No OpenPIC found !\n");
+ return;
+ }
+ OpenPIC = (volatile struct OpenPIC *)OpenPIC_Addr;
if ( ppc_md.progress ) ppc_md.progress("openpic enter",0x122);
@@ -194,179 +252,180 @@
OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
NumSources = ((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1;
- if ( _machine != _MACH_Pmac )
- {
- printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n", version,
- NumProcessors, NumSources, OpenPIC);
- timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);
- printk("OpenPIC timer frequency is ");
- if (timerfreq)
- printk("%d MHz\n", timerfreq>>20);
- else
- printk("not set\n");
+ printk("OpenPIC Version %s (%d CPUs and %d IRQ sources) at %p\n",
+ version, NumProcessors, NumSources, OpenPIC);
+ timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);
+ if (timerfreq)
+ printk("OpenPIC timer frequency is %d.%06d MHz\n",
+ timerfreq / 1000000, timerfreq % 1000000);
+
+ if (!main_pic)
+ return;
+
+ open_pic_irq_offset = offset;
+ chrp_int_ack_special = (volatile unsigned char*)chrp_ack;
+
+ /* Initialize timer interrupts */
+ if ( ppc_md.progress ) ppc_md.progress("openpic timer",0x3ba);
+ for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
+ /* Disabled, Priority 0 */
+ openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset);
+ /* No processor */
+ openpic_maptimer(i, 0);
}
-
- if ( main_pic )
- {
- /* Initialize timer interrupts */
- if ( ppc_md.progress ) ppc_md.progress("openpic timer",0x3ba);
- for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
- /* Disabled, Priority 0 */
- openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i);
- /* No processor */
- openpic_maptimer(i, 0);
- }
-
- /* Initialize IPI interrupts */
- if ( ppc_md.progress ) ppc_md.progress("openpic ipi",0x3bb);
- for (i = 0; i < OPENPIC_NUM_IPI; i++) {
- /* Disabled, Priority 8 */
- openpic_initipi(i, 8, OPENPIC_VEC_IPI+i);
- }
- find_ISUs();
- if ( _machine != _MACH_Pmac )
- {
- /* Initialize external interrupts */
- if ( ppc_md.progress ) ppc_md.progress("openpic ext",0x3bc);
- /* SIOint (8259 cascade) is special */
- openpic_initirq(0, 8, open_pic_irq_offset, 1, 1);
- openpic_mapirq(0, 1<<0);
- for (i = 1; i < NumSources; i++) {
- /* Enabled, Priority 8 */
- openpic_initirq(i, 8, open_pic_irq_offset+i, 0,
- i < OpenPIC_NumInitSenses ? OpenPIC_InitSenses[i] : 1);
- /* Processor 0 */
- openpic_mapirq(i, 1<<0);
- }
- }
- else
- {
- /* Prevent any interrupt from occuring during initialisation.
- * Hum... I believe this is not necessary, Apple does that in
- * Darwin's PowerExpress code.
- */
- openpic_set_priority(0, 0xf);
-
- /* First disable all interrupts and map them to CPU 0 */
- for (i = 0; i < NumSources; i++) {
- openpic_disable_irq(i);
- openpic_mapirq(i, 1<<0);
- }
-
- /* If we use the device tree, then lookup all interrupts and
- * initialize them according to sense infos found in the tree
- */
- if (use_of_interrupt_tree) {
- struct device_node* np = find_all_nodes();
- while(np) {
- int j, pri;
- pri = strcmp(np->name, "programmer-switch") ? 2 : 7;
- for (j=0;j<np->n_intrs;j++) {
- openpic_initirq(np->intrs[j].line,
- pri,
- np->intrs[j].line,
- 0,
- np->intrs[j].sense);
- if (np->intrs[j].sense)
- irq_desc[np->intrs[j].line].status = IRQ_LEVEL;
- }
- np = np->next;
- }
- }
- }
-
- /* Initialize the spurious interrupt */
- if ( ppc_md.progress ) ppc_md.progress("openpic spurious",0x3bd);
- openpic_set_spurious(OPENPIC_VEC_SPURIOUS);
- if ( !(_machine & (_MACH_gemini|_MACH_Pmac)) )
- {
- if (request_irq(IRQ_8259_CASCADE, no_action, SA_INTERRUPT,
- "82c59 cascade", NULL))
- printk("Unable to get OpenPIC IRQ 0 for cascade\n");
- }
- openpic_set_priority(0, 0);
- openpic_disable_8259_pass_through();
+
+#ifdef CONFIG_SMP
+ /* Initialize IPI interrupts */
+ if ( ppc_md.progress ) ppc_md.progress("openpic ipi",0x3bb);
+ for (i = 0; i < OPENPIC_NUM_IPI; i++) {
+ /* Disabled, Priority 10..13 */
+ openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset);
+ /* IPIs are per-CPU */
+ irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
+ irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
+ }
+#endif
+
+ find_ISUs();
+
+ /* Initialize external interrupts */
+ if (ppc_md.progress) ppc_md.progress("openpic ext",0x3bc);
+
+ openpic_set_priority(0xf);
+
+ /* SIOint (8259 cascade) is special */
+ if (offset) {
+ openpic_initirq(0, 8, offset, 1, 1);
+ openpic_mapirq(0, 1<<0);
}
- if ( ppc_md.progress ) ppc_md.progress("openpic exit",0x222);
+
+ /* Init all external sources */
+ for (i = 1; i < NumSources; i++) {
+ int pri, sense;
+
+ /* the bootloader may have left it enabled (bad !) */
+ openpic_disable_irq(i+offset);
+
+ pri = (i == programmer_switch_irq)? 9: 8;
+ sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: 1;
+ if (sense)
+ irq_desc[i+offset].status = IRQ_LEVEL;
+
+ /* Enabled, Priority 8 or 9 */
+ openpic_initirq(i, pri, i+offset, !sense, sense);
+ /* Processor 0 */
+ openpic_mapirq(i, 1<<0);
+ }
+
+ /* Init descriptors */
+ for (i = offset; i < NumSources + offset; i++)
+ irq_desc[i].handler = &open_pic;
+
+ /* Initialize the spurious interrupt */
+ if (ppc_md.progress) ppc_md.progress("openpic spurious",0x3bd);
+ openpic_set_spurious(OPENPIC_VEC_SPURIOUS+offset);
+
+ /* Initialize the cascade */
+ if (offset) {
+ if (request_irq(offset, no_action, SA_INTERRUPT,
+ "82c59 cascade", NULL))
+ printk("Unable to get OpenPIC IRQ 0 for cascade\n");
+ }
+ openpic_set_priority(0);
+ openpic_disable_8259_pass_through();
+
+ if (ppc_md.progress) ppc_md.progress("openpic exit",0x222);
}
+#ifdef CONFIG_POWER3
+void openpic_setup_ISU(int isu_num, unsigned long addr)
+{
+ if (isu_num >= OPENPIC_MAX_ISU)
+ return;
+ ISU[isu_num] = (OpenPIC_SourcePtr) ioremap(addr, 0x400);
+ if (isu_num >= NumISUs)
+ NumISUs = isu_num + 1;
+}
+#endif
+
void find_ISUs(void)
{
-#ifdef CONFIG_PPC64BRIDGE
- /* hardcode this for now since the IBM 260 is the only thing with
- * a distributed openpic right now. -- Cort
+#ifdef CONFIG_POWER3
+ /* Use /interrupt-controller/reg and
+ * /interrupt-controller/interrupt-ranges from OF device tree
+ * the ISU array is setup in chrp_pci.c in ibm_add_bridges
+ * as a result
+ * -- tgall
+ */
+
+ /* basically each ISU is a bus, and this assumes that
+ * open_pic_isu_count interrupts per bus are possible
+ * ISU == Interrupt Source
*/
- ISU = (OpenPIC_Source *)0xfeff7c00;
- NumSources = 0x10;
+ NumSources = NumISUs * 0x10;
+
#else
/* for non-distributed OpenPIC implementations it's in the IDU -- Cort */
- ISU = (OpenPIC_Source *)OpenPIC->Source;
+ ISU[0] = (OpenPIC_Source *)OpenPIC->Source;
#endif
}
-void openpic_reset(void)
+static inline void openpic_reset(void)
{
openpic_setfield(&OpenPIC->Global.Global_Configuration0,
OPENPIC_CONFIG_RESET);
}
-void openpic_enable_8259_pass_through(void)
+static inline void openpic_enable_8259_pass_through(void)
{
openpic_clearfield(&OpenPIC->Global.Global_Configuration0,
OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
}
-void openpic_disable_8259_pass_through(void)
+static void openpic_disable_8259_pass_through(void)
{
openpic_setfield(&OpenPIC->Global.Global_Configuration0,
OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
}
-#ifndef __i386__
/*
* Find out the current interrupt
*/
-u_int openpic_irq(u_int cpu)
+static u_int openpic_irq(void)
{
u_int vec;
+ DECL_THIS_CPU;
- check_arg_cpu(cpu);
+ CHECK_THIS_CPU;
vec = openpic_readfield(&OpenPIC->THIS_CPU.Interrupt_Acknowledge,
OPENPIC_VECTOR_MASK);
return vec;
}
-#endif
-#ifndef __powerpc__
-void openpic_eoi(void)
-#else
-void openpic_eoi(u_int cpu)
-#endif
+static void openpic_eoi(void)
{
- check_arg_cpu(cpu);
+ DECL_THIS_CPU;
+
+ CHECK_THIS_CPU;
openpic_write(&OpenPIC->THIS_CPU.EOI, 0);
/* Handle PCI write posting */
(void)openpic_read(&OpenPIC->THIS_CPU.EOI);
}
-#ifndef __powerpc__
-u_int openpic_get_priority(void)
-#else
-u_int openpic_get_priority(u_int cpu)
-#endif
+static inline u_int openpic_get_priority(void)
{
+ DECL_THIS_CPU;
+
CHECK_THIS_CPU;
return openpic_readfield(&OpenPIC->THIS_CPU.Current_Task_Priority,
OPENPIC_CURRENT_TASK_PRIORITY_MASK);
}
-#ifndef __powerpc__
-void openpic_set_priority(u_int pri)
-#else
-void openpic_set_priority(u_int cpu, u_int pri)
-#endif
+static void openpic_set_priority(u_int pri)
{
+ DECL_THIS_CPU;
+
CHECK_THIS_CPU;
check_arg_pri(pri);
openpic_writefield(&OpenPIC->THIS_CPU.Current_Task_Priority,
@@ -376,24 +435,43 @@
/*
* Get/set the spurious vector
*/
-u_int openpic_get_spurious(void)
+static inline u_int openpic_get_spurious(void)
{
return openpic_readfield(&OpenPIC->Global.Spurious_Vector,
OPENPIC_VECTOR_MASK);
}
-void openpic_set_spurious(u_int vec)
+static void openpic_set_spurious(u_int vec)
{
check_arg_vec(vec);
openpic_writefield(&OpenPIC->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
vec);
}
+#ifdef CONFIG_SMP
+/*
+ * Convert a cpu mask from logical to physical cpu numbers.
+ */
+static inline u32 physmask(u32 cpumask)
+{
+ int i;
+ u32 mask = 0;
+
+ for (i = 0; i < smp_num_cpus; ++i, cpumask >>= 1)
+ mask |= (cpumask & 1) << smp_hw_index[i];
+ return mask;
+}
+#else
+#define physmask(cpumask) (cpumask)
+#endif
+
void openpic_init_processor(u_int cpumask)
{
- openpic_write(&OpenPIC->Global.Processor_Initialization, cpumask);
+ openpic_write(&OpenPIC->Global.Processor_Initialization,
+ physmask(cpumask));
}
+#ifdef CONFIG_SMP
/*
* Initialize an interprocessor interrupt (and disable it)
*
@@ -401,35 +479,55 @@
* pri: interrupt source priority
* vec: the vector it will produce
*/
-void openpic_initipi(u_int ipi, u_int pri, u_int vec)
+static void __init openpic_initipi(u_int ipi, u_int pri, u_int vec)
{
- check_arg_timer(ipi);
+ check_arg_ipi(ipi);
check_arg_pri(pri);
check_arg_vec(vec);
- openpic_safe_writefield(&OpenPIC->Global.IPI_Vector_Priority(ipi),
+ openpic_safe_writefield_IPI(&OpenPIC->Global.IPI_Vector_Priority(ipi),
OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
(pri << OPENPIC_PRIORITY_SHIFT) | vec);
}
/*
* Send an IPI to one or more CPUs
+ *
+ * Externally called, however, it takes an IPI number (0...OPENPIC_NUM_IPI)
+ * and not a system-wide interrupt number
*/
-#ifndef __powerpc__
void openpic_cause_IPI(u_int ipi, u_int cpumask)
-#else
-void openpic_cause_IPI(u_int cpu, u_int ipi, u_int cpumask)
-#endif
{
+ DECL_THIS_CPU;
+
CHECK_THIS_CPU;
check_arg_ipi(ipi);
- openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi), cpumask);
+ openpic_write(&OpenPIC->THIS_CPU.IPI_Dispatch(ipi),
+ physmask(cpumask));
}
-void openpic_enable_IPI(u_int ipi)
+void openpic_request_IPIs(void)
{
- check_arg_ipi(ipi);
- openpic_clearfield(&OpenPIC->Global.IPI_Vector_Priority(ipi),
- OPENPIC_MASK);
+ int i;
+
+ /*
+ * Make sure this matches what is defined in smp.c for
+ * smp_message_{pass|recv}() or what shows up in
+ * /proc/interrupts will be wrong!!! --Troy */
+
+ if (OpenPIC == NULL)
+ return;
+
+ request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset,
+ openpic_ipi_action, 0, "IPI0 (call function)", 0);
+ request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+1,
+ openpic_ipi_action, 0, "IPI1 (reschedule)", 0);
+ request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+2,
+ openpic_ipi_action, 0, "IPI2 (invalidate tlb)", 0);
+ request_irq(OPENPIC_VEC_IPI+open_pic_irq_offset+3,
+ openpic_ipi_action, 0, "IPI3 (xmon break)", 0);
+
+ for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
+ openpic_enable_ipi(OPENPIC_VEC_IPI+open_pic_irq_offset+i);
}
/*
@@ -437,21 +535,31 @@
*
* Get IPI's working and start taking interrupts.
* -- Cort
- */
-void do_openpic_setup_cpu(void)
+ */
+static spinlock_t openpic_setup_lock __initdata = SPIN_LOCK_UNLOCKED;
+
+void __init do_openpic_setup_cpu(void)
{
int i;
-
- for ( i = 0; i < OPENPIC_NUM_IPI ; i++ )
- openpic_enable_IPI(i);
-#if 0
- /* let the openpic know we want intrs */
- for ( i = 0; i < NumSources ; i++ )
- openpic_mapirq(i, openpic_read(ISU[i].Destination)
- | (1<<smp_processor_id()) );
-#endif
- openpic_set_priority(smp_processor_id(), 0);
+ u32 msk = 1 << smp_hw_index[smp_processor_id()];
+
+ spin_lock(&openpic_setup_lock);
+
+#ifdef CONFIG_IRQ_ALL_CPUS
+ /* let the openpic know we want intrs. default affinity
+ * is 0xffffffff until changed via /proc
+ * That's how it's done on x86. If we want it differently, then
+ * we should make sure we also change the default values of irq_affinity
+ * in irq.c.
+ */
+ for (i = 0; i < NumSources ; i++)
+ openpic_mapirq(i, openpic_read(&GET_ISU(i).Destination) | msk);
+#endif /* CONFIG_IRQ_ALL_CPUS */
+ openpic_set_priority(0);
+
+ spin_unlock(&openpic_setup_lock);
}
+#endif /* CONFIG_SMP */
/*
* Initialize a timer interrupt (and disable it)
@@ -460,7 +568,7 @@
* pri: interrupt source priority
* vec: the vector it will produce
*/
-void openpic_inittimer(u_int timer, u_int pri, u_int vec)
+static void __init openpic_inittimer(u_int timer, u_int pri, u_int vec)
{
check_arg_timer(timer);
check_arg_pri(pri);
@@ -473,37 +581,99 @@
/*
* Map a timer interrupt to one or more CPUs
*/
-void openpic_maptimer(u_int timer, u_int cpumask)
+static void __init openpic_maptimer(u_int timer, u_int cpumask)
{
check_arg_timer(timer);
- openpic_write(&OpenPIC->Global.Timer[timer].Destination, cpumask);
+ openpic_write(&OpenPIC->Global.Timer[timer].Destination,
+ physmask(cpumask));
}
+
/*
- * Enable/disable an interrupt source
+ *
+ * All functions below take an offset'ed irq argument
+ *
*/
-void openpic_enable_irq(u_int irq)
+
+
+/*
+ * Enable/disable an external interrupt source
+ *
+ * Externally called, irq is an offseted system-wide interrupt number
+ */
+static void openpic_enable_irq(u_int irq)
{
check_arg_irq(irq);
- openpic_clearfield(&ISU[irq - open_pic_irq_offset].Vector_Priority, OPENPIC_MASK);
+
+ /*
+ * Never want to disable a timer or ipi irq
+ * (only want to disable irqs within an ISU).
+ */
+ if (((irq >= OPENPIC_VEC_IPI+open_pic_irq_offset) &&
+ (irq < OPENPIC_VEC_IPI+open_pic_irq_offset+OPENPIC_NUM_IPI)) ||
+ ((irq >= OPENPIC_VEC_TIMER+open_pic_irq_offset) &&
+ (irq < OPENPIC_VEC_TIMER+open_pic_irq_offset+OPENPIC_NUM_TIMERS)))
+ {
+ /* silently ignore the enable of the timer or ipi irq. */
+ return;
+ }
+
+
+ openpic_clearfield(&GET_ISU(irq - open_pic_irq_offset).Vector_Priority, OPENPIC_MASK);
/* make sure mask gets to controller before we return to user */
do {
mb(); /* sync is probably useless here */
- } while(openpic_readfield(&ISU[irq - open_pic_irq_offset].Vector_Priority,
+ } while(openpic_readfield(&GET_ISU(irq - open_pic_irq_offset).Vector_Priority,
OPENPIC_MASK));
}
-void openpic_disable_irq(u_int irq)
+static void openpic_disable_irq(u_int irq)
{
+ u32 vp;
+
check_arg_irq(irq);
- openpic_setfield(&ISU[irq - open_pic_irq_offset].Vector_Priority, OPENPIC_MASK);
+ /*
+ * Never want to disable a timer or ipi irq
+ * (only want to disable irqs within an ISU).
+ */
+ if (((irq >= OPENPIC_VEC_IPI+open_pic_irq_offset) &&
+ (irq < OPENPIC_VEC_IPI+open_pic_irq_offset+OPENPIC_NUM_IPI)) ||
+ ((irq >= OPENPIC_VEC_TIMER+open_pic_irq_offset) &&
+ (irq < OPENPIC_VEC_TIMER+open_pic_irq_offset+OPENPIC_NUM_TIMERS)))
+ {
+ panic("openpic_disable_irq - disabling non-ISU irq");
+ }
+
+
+ openpic_setfield(&GET_ISU(irq - open_pic_irq_offset).Vector_Priority, OPENPIC_MASK);
/* make sure mask gets to controller before we return to user */
do {
mb(); /* sync is probably useless here */
- } while(!openpic_readfield(&ISU[irq - open_pic_irq_offset].Vector_Priority,
- OPENPIC_MASK));
+ vp = openpic_readfield(&GET_ISU(irq - open_pic_irq_offset).Vector_Priority,
+ OPENPIC_MASK | OPENPIC_ACTIVITY);
+ } while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
}
+#ifdef CONFIG_SMP
+/*
+ * Enable/disable an IPI interrupt source
+ *
+ * Externally called, irq is an offseted system-wide interrupt number
+ */
+void openpic_enable_ipi(u_int irq)
+{
+ irq -= (OPENPIC_VEC_IPI+open_pic_irq_offset);
+ check_arg_ipi(irq);
+ openpic_clearfield_IPI(&OpenPIC->Global.IPI_Vector_Priority(irq), OPENPIC_MASK);
+
+}
+void openpic_disable_ipi(u_int irq)
+{
+ /* NEVER disable an IPI... that's just plain wrong! */
+}
+
+#endif
+
/*
* Initialize an interrupt source (and disable it!)
*
@@ -513,12 +683,9 @@
* pol: polarity (1 for positive, 0 for negative)
* sense: 1 for level, 0 for edge
*/
-void openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
+static void openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
{
- check_arg_irq(irq);
- check_arg_pri(pri);
- check_arg_vec(vec);
- openpic_safe_writefield(&ISU[irq].Vector_Priority,
+ openpic_safe_writefield(&GET_ISU(irq).Vector_Priority,
OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
(pri << OPENPIC_PRIORITY_SHIFT) | vec |
@@ -530,10 +697,9 @@
/*
* Map an interrupt source to one or more CPUs
*/
-void openpic_mapirq(u_int irq, u_int cpumask)
+static void openpic_mapirq(u_int irq, u_int physmask)
{
- check_arg_irq(irq);
- openpic_write(&ISU[irq].Destination, cpumask);
+ openpic_write(&GET_ISU(irq).Destination, physmask);
}
/*
@@ -541,10 +707,92 @@
*
* sense: 1 for level, 0 for edge
*/
-void openpic_set_sense(u_int irq, int sense)
+static inline void openpic_set_sense(u_int irq, int sense)
{
- check_arg_irq(irq);
- openpic_safe_writefield(&ISU[irq].Vector_Priority,
+ openpic_safe_writefield(&GET_ISU(irq).Vector_Priority,
OPENPIC_SENSE_LEVEL,
(sense ? OPENPIC_SENSE_LEVEL : 0));
}
+
+/* No spinlocks, should not be necessary with the OpenPIC
+ * (1 register = 1 interrupt and we have the desc lock).
+ */
+static void openpic_ack_irq(unsigned int irq_nr)
+{
+#if 1 /* masking should be unnecessary, but I still get spurrious */
+ openpic_disable_irq(irq_nr);
+#endif
+ if ((irq_desc[irq_nr].status & IRQ_LEVEL) == 0)
+ openpic_eoi();
+}
+
+static void openpic_end_irq(unsigned int irq_nr)
+{
+ if ((irq_desc[irq_nr].status & IRQ_LEVEL) != 0)
+ openpic_eoi();
+
+#if 1 /* masking should be unnecessary, but I still get spurrious */
+ if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+ openpic_enable_irq(irq_nr);
+#endif
+}
+
+static void openpic_set_affinity(unsigned int irq_nr, unsigned long cpumask)
+{
+ openpic_mapirq(irq_nr - open_pic_irq_offset, physmask(cpumask));
+}
+
+#ifdef CONFIG_SMP
+static void openpic_ack_ipi(unsigned int irq_nr)
+{
+}
+
+static void openpic_end_ipi(unsigned int irq_nr)
+{
+ /* IPIs are marked IRQ_PER_CPU. This has the side effect of
+ * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
+ * applying to them. We EOI them late to avoid re-entering.
+ * however, I'm wondering if we could simply let them have the
+ * SA_INTERRUPT flag and let them execute with all interrupts OFF.
+ * This would have the side effect of either running cross-CPU
+ * functions with interrupts off, or we can re-enable them explicitely
+ * with a __sti() in smp_call_function_interrupt(), since
+ * smp_call_function() is protected by a spinlock.
+ * Or maybe we shouldn't set the IRQ_PER_CPU flag on cross-CPU
+ * function calls IPI at all but that would make a special case.
+ */
+ openpic_eoi();
+}
+
+static void openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
+{
+ smp_message_recv(cpl-OPENPIC_VEC_IPI-open_pic_irq_offset, regs);
+}
+
+#endif /* CONFIG_SMP */
+
+/* This one may be merged with PReP and CHRP */
+int
+openpic_get_irq(struct pt_regs *regs)
+{
+ extern int i8259_irq(int cpu);
+
+ int irq = openpic_irq();
+
+ /* Management of the cascade should be moved out of here */
+ if (open_pic_irq_offset && irq == open_pic_irq_offset)
+ {
+ /*
+ * This magic address generates a PCI IACK cycle.
+ */
+ if ( chrp_int_ack_special )
+ irq = *chrp_int_ack_special;
+ else
+ irq = i8259_irq( smp_processor_id() );
+ openpic_eoi();
+ }
+ if (irq == OPENPIC_VEC_SPURIOUS + open_pic_irq_offset)
+ irq = -1;
+ return irq;
+}
+
FUNET's LINUX-ADM group, linux-adm@nic.funet.fi
TCL-scripts by Sam Shen (who was at: slshen@lbl.gov)