/************************************************************************/
/* Wait state generator pal for slow I/O devices.			*/
/*									*/
/*  2 wait states for SCSI psuedo dma					*/
/*  3 wait states for SCSI register select				*/
/*  7 wait states for EPROM bus cycles.					*/
/*  7 wait states for ICU & DUART bus cycles.				*/
/*   1 wait states of 'front porch' on IORD and IOWR and then 6		*/
/*   T-states for the IORD and IOWR bus cycles. A 74AS646 device	*/
/*   latches data from the peripheral device during a read cycle, thus	*/
/*   enabling the IORD signal to be deasserted 1-T state prior to the	*/
/*   last T2 T-state. This guarantees sufficient chip select and	*/
/*   address hold time after an IORD.					*/
/************************************************************************/

#define DESIGNER George Scolaro (C) 1988,89,90
#define REVISION 01	1/14/89
#define PARTNUM U38

wait(	in	bclk,		/* 32532 system clock */
		!eprom,		/* eprom select */
		!scsi,		/* scsi select */
		!bmt,		/* begin memory transaction */
		!ddin,		/* data direction */
		!slow,		/* slow peripheral cycle */
		drq,		/* scsi dma request */
		scsii,		/* scsi interrupt */
		a22,		/* address line 22 */
		!oe;
	out
		!dack,		/* scsi dma acknowledge */
		!eop;		/* eop to scsi on last byte transfer */
	reg
		!nrdy,		/* not ready to 32532 */
		!d0..2,		/* internal counter terms */
		!iord,		/* I/O read strobe */
		!iowr;		/* I/O write strobe */
)
{

group	state[d0, d1, d2, nrdy];

#define idle	0b0000
#define idlew	0b0001
#define wait1	0b0011
#define wait2	0b0101
#define wait3	0b0111
#define wait4	0b1001
#define wait5	0b1011
#define	wait6	0b1101
#define	wait7	0b1111

state[].ck	= bclk;
state[].oe	= oe;
iord.ck		= bclk;
iord.oe		= oe;
iowr.ck		= bclk;
iowr.oe		= oe;
eop.oe		= 1;
dack.oe		= 1;

int iocycle;


iocycle = (state[] == wait1 | state[] == wait2 | state[] == wait3
	 | state[] == wait4 | state[] == wait5 | state[] == wait6)
	| bmt & slow & scsi
	| bmt & !slow & scsi & (drq | scsii)
	| (state[] == idlew) & (drq | scsii);


eop	= iord & !slow & scsi & a22	/* scsi eop on last byte transfer */
	| iowr & !slow & scsi & a22;

dack	= iord & !slow & scsi		/* scsi dma read/write access */
	| iowr & !slow & scsi;
	
iord.d	= ddin & iocycle;

iowr.d	= !ddin & iocycle;

switch (state[])	{

case idle:
	if (bmt & slow)
		state[] = wait1;
	else if (bmt & !slow & scsi & !drq & !scsii)
		state[] = idlew;		/* wait till data ready */
	else if (bmt & !slow & scsi & (drq | scsii))
		state[] = wait1;
	else
		state[] = idle;
	break;

case	idlew:
	if (drq | scsii)
		state[] = wait1;	/* scsi data now ready */
	else if (!(!slow & scsi))
		state[] = idle;		/* exit, if reset */
	else
		state[] = idlew;
	break;

case wait1:
	if (!slow & scsi)
		state[] = wait7;	/* 2 wait states for scsi dma */
	else
		state[] = wait2;
	break;

case wait2:
	if (scsi)
		state[] = wait7;	/* 3 wait states for scsi polled */
	else
		state[] = wait3;
	break;

case wait3:
	state[] = wait4;
	break;

case wait4:
	state[] = wait5;
	break;

case wait5:
	state[] = wait6;
	break;

case wait6:
	state[] = wait7;
	break;

case wait7:
	state[] = idle;
	break;
}

putpart("p16r6", "wait",
	bclk, eprom, scsi, bmt, ddin, slow, drq, scsii, a22, GND,
	oe, dack, nrdy, d0, d1, d2, iord, iowr, eop, VCC);
}
