/************************************************************************/
/* This Pal generates 2 bank selects for up to 8 megabytes of dram,	*/
/* utilizing 1 megabyte DRAM SIMMS. It also generates the 4 CAS selects	*/
/* based upon refresh and byte enables.					*/
/************************************************************************/
/*  Allowable Target Device Types:	PAL20L8D			*/
/************************************************************************/

#define DESIGNER George Scolaro	(C) 1988,89,90
#define REVISION 01 	05/07/88
#define PARTNUM U19

dramen(	in	!be0l,		/* latched byte enables */
		!be1l,
		!be2l,
		!be3l,
		!rfcyc,		/* doing a refresh cycle */
		!bmt,		/* begin memory transaction */
		!cas,		/* cas from DRAMC pal */
		banks,		/* dram bank select, A22 or A24 */
		qo0,		/* two phase signals */
		qo1,
		!hsadr,		/* high speed access to dram in progress */
		!conf,		/* bus cycle confirmed */
		!ddin,		/* data direction from 32532 */
		!ras,		/* ras for drams */
		!rfrqi,		/* refresh request is pending */
		!ddinl;		/* /bclk latched ddin */
	out
		!cas0,		/* cas 0, output only */
		!cas3;		/* cas 3, output only */
	io
		!bank0,		/* bank 0, 0 - 3 megabytes */
		!bank1,		/* bank 1, 4 - 7 megabytes */
		!cas1,		/* cas 1 */
		!cas2;		/* cas 2 */
)
{

cas0.oe	= 1;
cas1.oe	= 1;
cas2.oe = 1;
cas3.oe = 1;
bank0.oe = 1;
bank1.oe = 1;

cas0	= cas & rfcyc
	| cas & !ddin & be0l
	| hsadr & conf & ddin & bmt & !rfrqi & !rfcyc & ras /* fast cas */
	| cas1 & hsadr & conf & ddin & !cas & !rfcyc
	| cas & ddinl & qo0
	| cas & ddinl & qo1;

cas1	= cas & rfcyc
	| cas & !ddin & be1l
	| hsadr & conf & ddin & bmt & !rfrqi & !rfcyc & ras /* fast cas */
	| cas1 & hsadr & conf & ddin & !cas & !rfcyc
	| cas & ddinl & qo0
	| cas & ddinl & qo1;

cas2	= cas & rfcyc
	| cas & !ddin & be2l
	| hsadr & conf & ddin & bmt & !rfrqi & !rfcyc & ras /* fast cas */
	| cas1 & hsadr & conf & ddin & !cas & !rfcyc
	| cas & ddinl & qo0
	| cas & ddinl & qo1;

cas3	= cas & rfcyc
	| cas & !ddin & be3l
	| hsadr & conf & ddin & bmt & !rfrqi & !rfcyc & ras /* fast cas */
	| cas1 & hsadr & conf & ddin & !cas & !rfcyc
	| cas & ddinl & qo0
	| cas & ddinl & qo1;

bank0	= !banks & !ras
	| bank0 & !bank1
	| rfcyc;

bank1	=  banks & !ras
	| bank1 & !bank0
	| rfcyc;

putpart("p20l8", "dramen",
	be0l, be1l, be2l, be3l, rfcyc, bmt, cas, banks, qo0, qo1,
	hsadr, GND,
	conf, ddin, cas0, bank1, cas1, cas2, bank0, ras, rfrqi,
	cas3, ddinl, VCC);
}
