/******************************************************************************
 * Copyright (c) ETSI 2017.
 *
 * This file is subject to copyrights owned by ETSI. Non-exclusive permission
 * is hereby granted, free of charge, to copy, reproduce and amend this file
 * under the following conditions: It is provided "as is", without warranty of any
 * kind, expressed or implied.
 * 
 * ETSI shall never be liable for any claim, damages, or other liability arising
 * from its use or inability of use.This permission does not apply to any documentation
 * associated with this file for which ETSI keeps all rights reserved. The present
 * copyright notice shall be included in all copies of whole or part of this
 * file and shall not imply any sub-license right.
 *
 * Modified by: Adrien Kirjak
 *
 ** @version  0.0.1
 ** @purpose  1:19.6, Ensure that the IUT properly evaluates do-while statements
 ** @verdict  pass  accept, ttcn3verdict:pass
 ***************************************************/
module Sem_1906_do_while_statement_001 {
	
	type component GeneralComp {	
	}
	
	testcase TC_Sem_1906_do_while_statement_001 () runs on GeneralComp{
		var integer v_j:=1;
		 
		do {
		  	v_j:=v_j+1;	
		} while(v_j<10);
		 
		if( v_j==10 ) { setverdict(pass); }
		else  { setverdict(fail); }
	  
	}

	control{

		execute(TC_Sem_1906_do_while_statement_001());

	}

}
