/******************************************************************************
 * Copyright (c) ETSI 2017.
 *
 * This file is subject to copyrights owned by ETSI. Non-exclusive permission
 * is hereby granted, free of charge, to copy, reproduce and amend this file
 * under the following conditions: It is provided "as is", without warranty of any
 * kind, expressed or implied.
 * 
 * ETSI shall never be liable for any claim, damages, or other liability arising
 * from its use or inability of use.This permission does not apply to any documentation
 * associated with this file for which ETSI keeps all rights reserved. The present
 * copyright notice shall be included in all copies of whole or part of this
 * file and shall not imply any sub-license right.
 *
 * Modified by: Adrien Kirjak
 *
 ** @version  0.0.1
 ** @purpose  1:20.4, Validate that interleave statements are properly handled.
 ** @verdict  pass accept, ttcn3verdict:pass
 *****************************************************************/

module Sem_2004_InterleaveStatement_001 {

    type port loopbackPort message {
        inout MyMessageType
    } with {extension "internal"}

    type component GeneralComp {
        port loopbackPort pt_myPort1,pt_myPort2;
        timer t_timer;
    }

    type record MyMessageType {
        integer field1,
        charstring field2,
        boolean field3
    }
    
    altstep checkTimeout(timer t_timer){
        [] t_timer.timeout {
            setverdict(fail);
        }
    }

    testcase TC_Sem_2004_InterleaveStatement_001() runs on GeneralComp {

		connect(self:pt_myPort1, self:pt_myPort1);
		connect(self:pt_myPort2, self:pt_myPort2);
    
        template MyMessageType MySig1 := {1,"aaa",true};
        template MyMessageType MySig2 := {2,"bbb",true};
        template MyMessageType MySig3 := {3,"ccc",true};
    
	    activate(checkTimeout(t_timer));
        pt_myPort1.send(MyMessageType:{1, "aaa", true});
        t_timer.start(3.0);
    
        interleave {
            [] pt_myPort1.receive(MySig1)
            {
                pt_myPort2.send(MySig2);
                alt {
                    [] pt_myPort1.receive(MySig3) {
                        setverdict(pass);
                    }
                }
            }
            [] pt_myPort2.receive(MySig2)
            {
                pt_myPort1.send(MySig3);
            }
        }

    }

    control{
        execute(TC_Sem_2004_InterleaveStatement_001());
    }
}
