/******************************************************************************
 * Copyright (c) ETSI 2017.
 *
 * This file is subject to copyrights owned by ETSI. Non-exclusive permission
 * is hereby granted, free of charge, to copy, reproduce and amend this file
 * under the following conditions: It is provided "as is", without warranty of any
 * kind, expressed or implied.
 * 
 * ETSI shall never be liable for any claim, damages, or other liability arising
 * from its use or inability of use.This permission does not apply to any documentation
 * associated with this file for which ETSI keeps all rights reserved. The present
 * copyright notice shall be included in all copies of whole or part of this
 * file and shall not imply any sub-license right.
 *
 * Modified by: Adrien Kirjak
 *
 ** @version  0.0.1
 ** @purpose  1:9, Ensure that two component can be mapped by one system interface 
** @verdict  pass accept, noexecution
 ***************************************************/
 //Two components are mapped to the same system interface
module Syn_0902_Communication_ports_001{ 

    type port myPort message {
	  	inout integer
	} with {extension "internal"}
	
	type component MyTestSystemInterface
	{
 		port myPort messagePort;
	}
	
	// MyTestSystemInterface is the test system interface
	testcase TC_Syn_0902_Communication_ports_001() runs on MyTestSystemInterface system MyTestSystemInterface 		{
		// establishing the port connections
		var MyTestSystemInterface MycompA;
		var MyTestSystemInterface MycompB;	
		MycompA := MyTestSystemInterface.create;
		MycompB := MyTestSystemInterface.create;

		map(MycompA:messagePort, system:messagePort);
		map(MycompB:messagePort, system:messagePort);

		setverdict(pass);
	
	}

	control{
		execute(TC_Syn_0902_Communication_ports_001());
	}
}
