/******************************************************************************
 * Copyright (c) ETSI 2017.
 *
 * This file is subject to copyrights owned by ETSI. Non-exclusive permission
 * is hereby granted, free of charge, to copy, reproduce and amend this file
 * under the following conditions: It is provided "as is", without warranty of any
 * kind, expressed or implied.
 * 
 * ETSI shall never be liable for any claim, damages, or other liability arising
 * from its use or inability of use.This permission does not apply to any documentation
 * associated with this file for which ETSI keeps all rights reserved. The present
 * copyright notice shall be included in all copies of whole or part of this
 * file and shall not imply any sub-license right.
 *
 * Modified by: Adrien Kirjak
 *
 ** @version  0.0.1
 ** @purpose  1:9.1, Verify that a component ports can be mapped to TSI ports
 ** @verdict  pass accept, ttcn3verdict:pass
 ***************************************************/

/*    NOTE: figure 6(d): Ensure that component ports can be mapped to a TSI ports */

module Sem_0901_Communication_ports_011 {
  
    type port MyPort message {
        inout integer
    } with {extension "internal"}

    type component GeneralComp
    {
        port MyPort p1,p2;
    }

    type component MyComp
    {
        port MyPort p1,p2;
    }

	function checkMapped() runs on MyComp
	{
		if(p1.checkstate("Mapped") and p2.checkstate("Mapped")) {
			setverdict(pass,"Mapped");			
		} else {
			setverdict(fail,"Mapped");
		}
	}
	
    testcase TC_Sem_0901_Communication_ports_011() runs on MyComp system GeneralComp {
        
       map(self:p1, system:p1);
       map(self:p2, system:p2);
        
       checkMapped();
    }
	
    control{
        execute(TC_Sem_0901_Communication_ports_011());
    }
}
