/******************************************************************************
 * Copyright (c) ETSI 2017.
 *
 * This file is subject to copyrights owned by ETSI. Non-exclusive permission
 * is hereby granted, free of charge, to copy, reproduce and amend this file
 * under the following conditions: It is provided "as is", without warranty of any
 * kind, expressed or implied.
 * 
 * ETSI shall never be liable for any claim, damages, or other liability arising
 * from its use or inability of use.This permission does not apply to any documentation
 * associated with this file for which ETSI keeps all rights reserved. The present
 * copyright notice shall be included in all copies of whole or part of this
 * file and shall not imply any sub-license right.
 *
 * Modified by: Adrien Kirjak
 *
 ** @version  0.0.1
 ** @desc     Test cases for clause 5.3 ordering rules                     
 ** @purpose  1:5.3, Ensure that allowed any ordering with component definitions are supported
 ** @verdict  pass accept, ttcn3verdict:pass
 ***************************************************/
module Sem_0503_Ordering_002 {


type port loopbackPort message {
	  inout integer
} with {extension "internal"}

type component GeneralComp	//declarations inside a component can be in any order
{
 timer t_rec,t_rec2;
 var integer v_comp1:=0;
 port loopbackPort messagePortA;
 var integer v_comp2:=0;
}

testcase TC_Sem_0503_Ordering_002() runs on GeneralComp  {
    
     v_comp1 := 1;
     v_comp2 := v_comp1;
      if (v_comp2 == 1) {
	    setverdict(pass);
      }

}

control {
    execute(TC_Sem_0503_Ordering_002());
}

}
