<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE language SYSTEM "klayout_doc.dtd">

<doc>

  <title>The Net Tracing Feature</title>
  <keyword name="Net tracer"/>
  <keyword name="Connectivity"/>

  <h2-index/>

  <p>
  The net tracing function allows tracing of a net by detecting touching shapes that together form a conductive
  region. It features specification of a stack of metal (or in general "conductive") layers optionally connected through 
  via shapes. The net tracing algorithm will follow connections over the via shapes to form connections to other
  metal layers. The material footprint can be derived from single layout layers or a boolean combination of several
  layers. For example, this allows selecting source and drain regions of transistors by subtracting the poly region from the 
  active area region.
  </p>

  <h2>Single net tracing</h2>

  <p>
  This algorithm is intended for extracting single nets and employs an incremental extraction approach. Therefore 
  extraction of a single small net is comparatively fast while extraction of large nets such as power nets is considerably 
  slower compared to hierarchical LVS tools currently.
  </p>

  <p>
  The net tracing function can be found in the "Tools" menu. The user interface allows tracing of multiple nets which are stored 
  in a list of nets extracted. If labels are found on the nets, these are used to derive a net name. Beside that, the cells which
  are traversed in the net extraction are listed, so the cells being connected by this net can be identified.
  </p>

  <p>
  Before nets can be extracted, a layer stack must be specified. Press "Layer Stack" on the user interface to open the 
  layer stack dialog. Layers must be specified in the "layer/datatype" notation. The 
  via specification is optional. If no via layer is specified, both metal layer shapes are required to touch in order to form a 
  connection. If a via layer is specified, a via shape must be present to form the connection.
  </p>

  <p>
  KLayout allows specification of symbolic layers and to use boolean expressions. That way it is possible to 
  assign meaningful names to layers (i.e. "POLY" or "VIA1") and to use derived layers (i.e. "ACTIVE-POLY" for
  the source and drain regions of a CMOS transistor). Read more about these features in <link href="/about/connectivity.xml"/>
  and <link href="/about/symbolic_layers.xml"/>.
  </p>

  <p>
  If a layer stack has been defined, a net can be traced by pressing the "Trace Net" button and clicking on a point in the
  layout. Starting from shapes found under this point, the net is extracted and listed in the net list on the left side of the 
  net tracing dialog. If "Lock" is checked, another net can be traced by clicking at another point without having to press
  the "Trace Net" button again.
  </p>

  <p>
  The "Trace Path" function works similar but allows specification of two points and let the algorithm find the shortest connection
  (in terms of shape count, not geometrical length) between those points. If the points are not connected, a message is given
  which indicates that no path leads from one point to the other.
  </p>

  <p>
  The display of the nets can be configured in many ways. The configuration dialog is opened when "Configure" is pressed in 
  the trace net dialog. Beside the color and style of the markers used to display the net it can be specified if and how the window
  is changed to fit the net.
  </p>

  <h2>Tracing all nets</h2>

  <p>
  This algorithm is borrowed from the LVS feature, where the scenario is extended by device 
  recognition and netlist formation. In the context of the net tracer, nets consist of the 
  connected shapes but don't attach to devices. As LVS extracts all nets in one sweep, using
  this feature in the net tracer will deliver all nets at once. Although this is a richer
  information output, the tracing of all nets is typically faster then tracing a single, big
  net such as power nets. The LVS net extractor also supports hierarchical processing which
  gives a considerable performance improvement and more compact net representations.
  </p>

  <p>
  To extract all nets, use "Trace All Nets" from the "Tools" menu. It will start extracting
  the nets immediately. It will take the connectivity definition from the standard, single-net
  net tracer. You can edit this layer stack either from the single net tracer UI, from the technology
  manager or "Edit Layer Stack" from the "Tools" menu.
  </p>

  <p>
  After the net tracer has finished, the netlist browser dialog opens. In this dialog you
  can:
  </p>

  <ul>
    <li>Browser the circuit hierarchy (taken from the cell hierarchy) in the left half of the central 
    view.
    </li>
    <li>Browse the nets of the circuits in the right half of the view. Clicking on a net
    will highlight the net.
    </li>
    <li>Configure the net highlighting behavior. Use the "Configure" button.
    </li>
    <li>Export all or selected nets to layout, save the netlist (with shapes) to a file, load it back from a file and manage
    the netlist database. Use the "File" menu button in the right upper corner.
    </li>
    <li>Search for net names (if labeled) and circuits using the search edit box.
    </li>
    <li>Navigate through the history using the "back" and "forward" buttons at the top left.
    </li>
  </ul>

  <p>
  Extracted nets are written and read in a KLayout-specific format called "L2N" ("layout to netlist").
  This format contains both the nets and the shapes that make up a net. This way, the traced
  nets can be saved and retrieved later.
  </p>

</doc>

